Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
 
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link Controller Module
Register Descriptions
  MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
The BDLC supports the In-frame Response (IFR) feature of J1850 by 
setting these bits correctly. The four types of J1850 IFR are shown in 
Types of In-Frame Response. The purpose of the in-frame response 
modes is to allow single or multiple nodes to acknowledge receipt of 
the data by responding to a received message after they have seen 
the EOD symbol. For VPW modulation, the first bit of the IFR is 
always passive; therefore, an active normalization bit must be 
generated by the responder and sent prior to its ID/address byte. 
When there are multiple responders on the J1850 bus, only one 
normalization bit is sent which assists all other transmitting nodes to 
sync their responses. 
Figure 127 Types of In-Frame Response
TSIFR 
— Transmit Single Byte IFR with no CRC (Type 1 or 2)
This bit is used to request the BDLC to transmit the byte in the BDLC 
Data Register (DLCBDR) as a single byte IFR with no CRC. Typically, 
the byte transmitted is a unique identifier or address of the 
transmitting (responding) node.
1 = If this bit is set prior to a valid EOD being received with no CRC 
error, once the EOD symbol has been received the BDLC will 
attempt to transmit the appropriate normalization bit followed 
by the byte in the DLCBDR. 
SOF
Header Data Field CRC
EOD
Type 0 – No IFR
Header
Data Field CRC
EOD
Type 3 – Multiple Bytes From a Single Responder (with or without CRC)
Header Data Field CRC
EOD
Type 1 – Single Byte From a Single Responder (without CRC)
Header Data Field
CRC
EOD
Type 2 – Single Byte From Multiple Responders (without CRC)
ID1
ID n
IFR Data Field CRC
NB
NB
NB
ID
SOF
SOF SOF
EOF
EOD
EOF
EOD
EOF
EOD
EOF
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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