Datasheet

Background Debug Module (BDM)
Registers
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
The secure BDM firmware lookup table verifies that the on-chip
EEPROM and Flash EEPROM are erased. This being the case, the
UNSEC bit is set and the BDM program jumps to the start of the
standard BDM firmware lookup table and the secure BDM firmware
lookup table is turned off.
1 = the system is in a unsecured mode
0 = the system is in a secured mode
WARNING: When UNSEC is set, security is off and the user can change the state of
the secure bits in the on-chip Flash EEPROM. Note that if the user does
not change the state of the bits to “unsecured” mode, the system will be
secured again when it is next taken out of reset.
BDM CCR Holding
Register
(BDMCCR)
Read: All modes
Write: All modes
NOTE: When BDM is made active, the CPU stores the value of the CCR register
in the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to $D8 and not $D0 which is the reset value of the CCR
register.
When entering background debug mode, the BDM CCR holding register
is used to save the contents of the condition code register of the user’s
program. It is also used for temporary storage in the standard BDM
firmware mode. The BDM CCR holding register can be written to modify
the CCR value.
Address: $FF06
Bit 7 654321Bit 0
Read:
CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Write:
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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