Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Background Debug Module
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
Modes of Operation
BDM is available in all operating modes but must be enabled before
firmware commands are executed.
Some system peripherals may have a control bit which allows
suspending the peripheral function during background debug mode.
In special single-chip mode, background operation is enabled and active
out of reset. This allows programming a system with blank memory.
BDM is also active out of special peripheral mode reset and can be
turned off by clearing the BDMACT bit in the BDM status (BDMSTS)
register. This allows testing of the BDM memory space as well as the
user’s memory space.
NOTE:
The BDM serial system should not be used in special peripheral mode
since the CPU, which in other modes interfaces with the BDM to
relinquish control of the bus during a free cycle or a steal operation, is
not operating in this mode.
Normal Operation BDM operates the same in all normal modes.
Special Operation
Special single-chip
mode
BDM is enabled and active immediately out of reset. This allows
programming a system with blank memory.
Special peripheral
mode
BDM is enabled and active immediately out of reset. BDM can be
disabled by clearing the BDMACT bit in the BDM status (BDMSTS)
register. The BDM serial system should not be used in special peripheral
mode.
Emulation Modes In emulation modes, the BDM operates as in all normal modes.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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