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HCS12

Microcontrollers

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MC9S12E256

Data Sheet

MC9S12E256

Rev. 1.10

07/2012

Summary of content (610 pages)

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MC9S12E256 Data Sheet HCS12 Microcontrollers MC9S12E256 Rev. 1.10 07/2012 freescale.
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MC9S12E256 Data Sheet MC9S12E256 Rev. 1.10 07/2012 MC9S12E256 Data Sheet, Rev. 1.
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision History Date Revision Level November 10, 2005 1.07 Description New Data Sheet Table A-4.
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List of Chapters Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) . . . . . . . 21 Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) . . . . . . . . . . . . . . . 81 Chapter 3 Port Integration Module (PIM9E256V1) Block Description . . 121 Chapter 4 Clocks and Reset Generator (CRGV4) Block Description . . 167 Chapter 5 Oscillator (OSCV2) Block Description . . . . . . . . . . . . . . . . . .
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MC9S12E256 Data Sheet, Rev. 1.
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Section Number Title Page Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.1 1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 1.4.30 PS7 / SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.4.31 PS6 / SCK — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.32 PS5 / MOSI — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.33 PS4 / MISO — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Title Page 2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Memory Map and Register Definition . . .
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Section Number 3.5 3.6 Title Page 3.4.7 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 3.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 5 Oscillator (OSCV2) Block Description 5.1 5.2 5.3 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.1 7.2 7.3 7.4 7.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 8.6 Title Page 8.5.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 8.5.7 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 8.6.1 Description of Interrupt Operation . . . . . . . . . . .
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Section Number Title Page 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 13.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 13.6.2 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 15.2.2 TAGHI — High Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 15.2.3 TAGLO — Low Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 19.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Appendix A Electrical Characteristics A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 A.1.2 Power Supply . . .
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Section Number Title Page MC9S12E256 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) • • • • • • • Two 1-channel Digital-to-Analog Converters (DAC) — 8-bit resolution Analog-to-Digital Converter (ADC) — 16-channel module with 10-bit resolution — External conversion trigger capability Three 4-channel Timers (TIM) — Programmable input capture or output compare channels — Simple PWM mode — Counter modulo reset — External event counting — Gated time accumulation 6 PWM channels (PWM) — Programmable period and duty cycle — 8-bit 6-chann
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) • • • • 1.1.2 Operating frequency — 50MHz equivalent to 25MHz Bus Speed Internal 2.5V Regulator — Input voltage range from 2.97V to 5.5V — Low power mode capability — Includes low voltage reset (LVR) circuitry — Includes low voltage interrupt (LVI) circuitry 112-Pin LQFP or 80-Pin QFP package — Up to 90 I/O lines with 5V input and drive capability (112 pin package) — Up to two dedicated 5V input only lines (IRQ and XIRQ) — Sixteen 3.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) TIM1 PW10 PW11 PW12 PW13 PW14 PW15 IOC24 IOC25 IOC26 IOC27 Multiplexed Address/Data Bus PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PTB ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DDRB PTA DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DDRA ADC/DAC 3.3V/5V Voltage Reference VRH VRL I/O Driver 3.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.2 Device Memory Map Table 1-1 shows the device register map of the MC9S12E256 after reset. Figure 1-2 illustrates the device memory map with Flash and RAM. Table 1-1.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0000 0x0400 0x0000 1K Register Space 0x03FF Mappable to any 2K Boundary 0x4000 16K Bytes RAM 0x4000 Mappable to any 16K Boundary 0x7FFF 0x8000 0x8000 16K Page Window sixteen * 16K Flash EEPROM Pages EXT 0xBFFF 0xC000 0xC000 16K Fixed Flash EEPROM 0xFFFF 2K, 4K, 8K or 16K Protected Boot Sector 0xFF00 0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP VECTORS VECTORS EXPANDED SPECIAL SINGLE CHIP 0xFFFF BDM (If Active) The figure shows a usef
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.2.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0010 – 0x0014 MMC Map 1 of 4 (HCS12 Module Mapping Control) Address Name 0x0010 INITRM 0x0011 INITRG 0x0012 INITEE 0x0013 MISC 0x0014 MTST0 R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RAM15 RAM14 RAM13 RAM12 RAM11 REG14 REG13 REG12 REG11 EE15 EE14 EE13 EE12 EE11 0 0 0 0 Bit 7 6 5 0 W R W R Bit 2 Bit 1 0 0 0 0 0 0 EXSTR1 EXSTR0 ROMHM ROMON 4 3 2 1 Bit 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WRINT ADR3 AD
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x001A – 0x001B Miscellaneous Peripherals (Device User Guide) Address Name 0x001A PARTIDH 0x001B PARTIDL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W R W 0x001C – 0x001D MMC Map 3 of 4 (HCS12 Module Mapping Control, Device User Guide) Address Name 0x001C MEMSIZ0 0x001D MEMSIZ1 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reg_s
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0020 – 0x002F DBG (Including BKP) Map 1 of 1 (HCS12 Debug) (continued) Address 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F Name DBGCCH R — W DBGCCL R — W DBGC2 R BKPCT0 W DBGC3 R BKPCT1 W DBGCAX R BKP0X W DBGCAH R BKP0H W DBGCAL R BKP0L W DBGCBX R BKP1X W DBGCBH R BKP1H W DBGCBL R BKP1L W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0034 – 0x003F CRG (Clock and Reset Generator) Address Name 0x0034 SYNR 0x0035 REFDV 0x0036 CTFLG TEST ONLY 0x0037 CRGFLG 0x0038 CRGINT 0x0039 CLKSEL 0x003A PLLCTL 0x003B RTICTL 0x003C COPCTL 0x003D FORBYP TEST ONLY 0x003E CTCTL TEST ONLY 0x003F ARMCOP R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 TOUT7 TOUT6 TOUT5 TOUT4 TOUT
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0040 – 0x006F TIM0 (Timer 16 Bit 4 Channels) (Sheet 2 of 4) Address Name 0x0046 TSCR1 0x0047 TTOV 0x0048 TCTL1 0x0049 Reserved 0x004A TCTL3 0x004B Reserved 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 Reserved 0x0051 Reserved 0x0052 Reserved 0x0053 Reserved 0x0054 Reserved 0x0055 Reserved 0x0056 Reserved 0x0057 Reserved 0x0058 TC4 (hi) R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0040 – 0x006F TIM0 (Timer 16 Bit 4 Channels) (Sheet 3 of 4) Address Name 0x0059 TC4 (lo) 0x005A TC5 (hi) 0x005B TC5 (lo) 0x005C TC6 (hi) 0x005D TC6 (lo) 0x005E TC7 (hi) 0x005F TC7 (lo) 0x0060 PACTL 0x0061 PAFLG 0x0062 PACNT (hi) 0x0063 PACNT (lo) 0x0064 Reserved 0x0065 Reserved 0x0066 Reserved 0x0067 Reserved 0x0068 Reserved 0x0069 Reserved 0x006A Reserved 0x006B Reserved R W R W R W R W R W R W R W R Bit 7 Bi
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0040 – 0x006F TIM0 (Timer 16 Bit 4 Channels) (Sheet 4 of 4) Address Name 0x006C Reserved 0x006D Reserved 0x006E Reserved 0x006F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 W R W R W R W 0x0070 – 0x007F Reserved Address Name 0x0070– 0x007F Re
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0080 – 0x00AF ATD (Analog to Digital Converter 10 Bit 16 Channel) (Sheet 2 of 3) Address Name 0x008B ATDSTAT1 0x008C ATDDIEN0 0x008D ATDDIEN1 0x008E PORTAD0 0x008F PORTAD1 0x0090 ATDDR0H 0x0091 ATDDR0L 0x0092 ATDDR1H 0x0093 ATDDR1L 0x0094 ATDDR2H 0x0095 ATDDR2L 0x0096 ATDDR3H 0x0097 ATDDR3L 0x0098 ATDDR4H 0x0099 ATDDR4L 0x009A ATDDR5H 0x009B ATDDR5L 0x009C ATDDR6H 0x009D ATDDR6L R Bit 7 Bit 6 Bit 5 Bit 4 Bi
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0080 – 0x00AF ATD (Analog to Digital Converter 10 Bit 16 Channel) (Sheet 3 of 3) Address Name 0x009E ATDDR7H 0x009F ATDDR7L 0x00A0 ATDDR8H 0x00A1 ATDDR8L 0x00A2 ATDDR9H 0x00A3 ATDDR9L 0x00A4 ATDDR10H 0x00A5 ATDDR10L 0x00A6 ATDDR11H 0x00A7 ATDDR11L 0x00A8 ATDDR12H 0x00A9 ATDDR12L 0x00AA ATDDR13H 0x00AB ATDDR13L 0x00AC ATDDR14H 0x00AD ATDDR14L 0x00AE ATDDR15H 0x00AF ATDDR15L 1 2 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x00B0 – 0x00C7 Reserved Address Name 0x00B0– 0x00C7 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 W 0x00C8 – 0x00CF SCI0 (Asynchronous Serial Interface) Address Name 0x00C8 SCIBDH 0x00C9 SCIBDL 0x00CA SCICR1 0x00CB SCICR2 0x00CC SCISR1 0x00CD SCISR2 0x00CE SCIDRH 0x00CF SCIDRL 1 R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IREN TNP1 TNP0 SBR12 SBR11
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x00D0 – 0x00D7 SCI1 (Asynchronous Serial Interface) (continued) Address Name 0x00D5 SCISR2 0x00D6 SCIDRH 0x00D7 SCIDRL 1 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 TXPOL1 RXPOL1 BRK13 TXDIR 0 0 0 0 0 0 W R R8 W T8 Bit 0 RAF R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 TXPOL and RXPOL are available in version V04 of SCI 0x00D8 – 0x00DF SPI (Serial Peripheral Interface) Address Name 0x
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x00E0 – 0x00E7 IIC (Inter-IC Bus) (continued) Address Name 0x00E4 IBDR 0x00E5 Reserved 0x00E6 Reserved 0x00E7 Reserved R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W 0x00E8 – 0x00EF SCI2 (Asynchronous Serial Interface) Address Name 0x00E8 SCIBDH 0x00E9 SCIBDL 0x00EA SCICR1 0x00EB SCICR2 0x00EC SCISR1 0
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x00F0 – 0x00F3 DAC0 (Digital-to-Analog Converter) Address Name 0x00F0 DACC0 0x00F1 DACC1 0x00F2 DACD 0x00F3 DACD Bit 7 R W R Bit 6 Bit 5 Bit 4 DACTE 0 0 0 0 0 BIT7 BIT6 BIT7 BIT6 DACE Bit 3 Bit 2 Bit 1 Bit 0 DJM DSGN DACWAI DACOE 0 0 0 0 0 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Bit 3 Bit 2 Bit 1 Bit 0 DJM DSGN DACWAI DACOE W R W R W 0x00F4 – 0x00F7 DAC1 (Digital-to-Analog C
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0100 – 0x010F Flash Control Register (continued) Address Name 0x0105 FSTAT 0x0106 FCMD 0x0107 Reserved for Factory Test 0x0108 Reserved for Factory Test 0x0109 Reserved for Factory Test 0x010A Reserved for Factory Test 0x010B Reserved for Factory Test 0x010C Reserved 0x010D Reserved 0x010E Reserved 0x010F Reserved Bit 7 R W R CBEIF 0 CCIF Bit 5 Bit 4 PVIOL ACCERR Bit 3 0 Bit 2 BLANK Bit 1 Bit 0 0 0 0 0 0 0 0 0
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet 2 of 4) Address Name 0x0144 TCNT (hi) 0x0145 TCNT (lo) 0x0146 TSCR1 0x0147 TTOV 0x0148 TCTL1 0x0149 Reserved 0x014A TCTL3 0x014B Reserved 0x014C TIE 0x014D TSCR2 0x014E TFLG1 0x014F TFLG2 0x0150 Reserved 0x0151 Reserved 0x0152 Reserved 0x0153 Reserved 0x0154 Reserved 0x0155 Reserved 0x0156 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet 3 of 4) Address Name 0x0157 Reserved 0x0158 TC4 (hi) 0x0159 TC4 (lo) 0x015A TC5 (hi) 0x015B TC5 (lo) 0x015C TC6 (hi) 0x015D TC6 (lo) 0x015E TC7 (hi) 0x015F TC7 (lo) 0x0160 PACTL 0x0161 PAFLG 0x0162 PACNT (hi) 0x0163 PACNT (lo) 0x0164 Reserved 0x0165 Reserved 0x0166 Reserved 0x0167 Reserved 0x0168 Reserved 0x0169 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet 4 of 4) Address Name 0x016A Reserved 0x016B Reserved 0x016C Reserved 0x016D Reserved 0x016E Reserved 0x016F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0180 – 0x01AF TIM2 (Timer 16 Bit 4 Channels) (Sheet 2 of 3) Address Name 0x0189 Reserved 0x018A TCTL3 0x018B Reserved 0x018C TIE 0x018D TSCR2 0x018E TFLG1 0x018F TFLG2 0x0190 Reserved 0x0191 Reserved 0x0192 Reserved 0x0193 Reserved 0x0194 Reserved 0x0195 Reserved 0x0196 Reserved 0x0197 Reserved 0x0198 TC4 (hi) 0x0199 TC4 (lo) 0x015A TC5 (hi) 0x019B TC5 (lo) 0x019C TC6 (hi) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0180 – 0x01AF TIM2 (Timer 16 Bit 4 Channels) (Sheet 3 of 3) Address Name 0x019D TC6 (lo) 0x019E TC7 (hi) 0x019F TC7 (lo) 0x01A0 PACTL 0x01A1 PAFLG 0x01A2 PACNT (hi) 0x01A3 PACNT (lo) 0x01A4 Reserved 0x01A5 Reserved 0x01A6 Reserved 0x01A7 Reserved 0x01A8 Reserved 0x01A9 Reserved 0x01AA Reserved 0x01AB Reserved 0x01AC Reserved 0x01AD Reserved 0x01AE Reserved 0x01AF Reserved R W R W R W R Bit 7 Bit 6 Bit 5 Bit
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x01B0 – 0x01DF Reserved Address Name 0x01B0– 0x01DF Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 CON45 CON23 CON01 PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x01E0 – 0x01FF PWM (Pulse Width Modulator) (continued) Address Name 0x01F0 PWMCNT4 0x01F1 PWMCNT5 0x01F2 PWMPER0 0x01F3 PWMPER1 0x01F4 PWMPER2 0x01F5 PWMPER3 0x01F6 PWMPER4 0x01F7 PWMPER5 0x01F8 PWMDTY0 0x01F9 PWMDTY1 0x01FA PWMDTY2 0x01FB PWMDTY3 0x01FC PWMDTY4 0x01FD PWMDTY5 0x01FE PWMSDN 0x01FF Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 1 of 4) Address Name 0x0200 PMFCFG0 0x0201 PMFCFG1 0x0202 PMFCFG2 0x0203 PMFCFG3 0x0204 PMFFCTL 0x0205 PMFFPIN 0x0206 PMFFSTA 0x0207 PMFQSMP 0x0208 PMFDMPA 0x0209 PMFDMPB 0x020A PMFDMPC 0x020B Reserved 0x020C PMFOUTC 0x020D PMFOUTB 0x020E PMFDTMS 0x020F PMFCCTL 0x0210 PMFVAL0 0x0211 PMFVAL0 0x0212 PMFVAL1 R W R W R Bit 7 Bit 6 Bit 5 Bit 4
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 2 of 4) Address Name 0x0213 PMFVAL1 0x0214 PMFVAL2 0x0215 PMFVAL2 0x0216 PMFVAL3 0x0217 PMFVAL3 0x0218 PMFVAL4 0x0219 PMFVAL4 0x021A PMFVAL5 0x021B PMFVAL5 0x021C Reserved 0x021D Reserved 0x021E Reserved 0x021F Reserved 0x0220 PMFENCA 0x0221 PMFFQCA 0x0222 PMFCNTA 0x0223 PMFCNTA 0x0224 PMFMODA 0x0225 PMFMODA R W R W R W R W R W R W R W R W R
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 3 of 4) Address Name 0x0226 PMFDTMA 0x0227 PMFDTMA 0x0228 PMFENCB 0x0229 PMFFQCB 0x022A PMFCNTB 0x022B PMFCNTB 0x022C PMFMODB 0x022D PMFMODB 0x022E PMFDTMB 0x022F PMFDTMB 0x0230 PMFENCC 0x0231 PMFFQCC 0x0232 PMFCNTC 0x0233 PMFCNTC 0x0234 PMFMODC 0x0235 PMFMODC 0x0236 PMFDTMC 0x0237 PMFDTMC 0x0238 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 4 of 4) Address Name 0x0239 Reserved 0x023A Reserved 0x023B Reserved 0x023C Reserved 0x023D Reserved 0x023E Reserved 0x023F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0240 – 0x027F PIM (Port Interface Module) (Sheet 2 of 4) Address Name 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 Reserved 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP R W R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0240 – 0x027F PIM (Port Interface Module) (Sheet 3 of 4) Address Name 0x025D PPSP 0x025E Reserved 0x025F Reserved 0x0260 PTQ 0x0261 PTIQ 0x0262 DDRQ 0x0263 RDRQ 0x0264 PERQ 0x0265 PPSQ 0x0266 Reserved 0x0267 Reserved 0x0268 PTU 0x0269 PTIU 0x026A DDRU 0x026B RDRU 0x026C PERU 0x026D PPSU 0x026E MODRR 0x026F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 0x0240 – 0x027F PIM (Port Interface Module) (Sheet 4 of 4) Address Name 0x0270 PTAD(H) 0x0271 PTAD(L) 0x0272 PTIAD(H) 0x0273 PTIAD(L) 0x0274 DDRAD(H) 0x0275 DDRAD(L) 0x0276 RDRAD(H) 0x0277 RDRAD(L) 0x0278 PERAD(H) 0x0279 PERAD(L) 0x027A PPSAD(H) 0x027B PPSAD(L) 0x027C PIEAD(H) 0x027D PIEAD(L) 0x027E PIFAD(H) 0x027F PIFAD(L) R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTAD15 PTAD14 PTAD13 PTAD12
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.2.2 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B after reset. The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID numbers. Table 1-2.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12E256 80 QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07/KWAD07 PAD06/AN06/KWAD06 PAD05/AN05/KWAD05 PAD04/AN04/KWAD04 PAD03/AN03/KWAD03 PAD02/AN02/KWAD02 PAD01/AN01/KWAD01 PAD00/AN00/KWAD00 VSS2 VDD2 PS7/SS PS6/SCK PS5/MOSI PS4/MISO PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 IOC15/PT5 IOC16/PT6 IOC17/PT7 PW10/IOC24/PU0 PW11/IOC25/PU1 XCLKS/NOACC/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PW12/IOC26/P
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.3.2 Signal Properties Summary Table 1-4.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-4.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.4 1.4.1 Detailed Signal Descriptions EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 1.4.2 RESET — External Reset Pin RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.4.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7 PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free cycle”. This signal will assert when the CPU is not using the bus.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.4.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. PE5 is not available in the 80-pin package version. 1.4.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register. 1.4.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.4.19 PAD[15:0] / AN[15:0] / KWAD[15:0] — Port AD I/O Pins [15:0] PAD[15:0] are the analog inputs for the analog to digital converter (ADC). They can also be configured as general purpose digital input or output pin. When enabled as digital inputs or outputs, the PAD[15:0] can also be configured as Keypad Wake-up pins (KWU) and generate interrupts causing the MCU to exit STOP or WAIT mode.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.4.25 PM1 / DAO1 — Port M I/O Pin 1 PM1 is a general purpose input or output pin. When the Digital to Analog module 1 (DAC1) is enabled the PM1 pin is configured as the analog output DA01 of DAC1. While in reset and immediately out of reset the PM1 pin is configured as a high impedance input pin.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) a high impedance input pin. Consult Chapter 3, “Port Integration Module (PIM9E256V1) Block Description” and Chapter 9, “Serial Peripheral Interface (SPIV3) Block Description” for information about pin configurations. 1.4.31 PS6 / SCK — Port S I/O Pin 6 PS6 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS6 becomes the serial clock pin, SCK.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.4.36 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) transmitter is enabled the PS1 pin is configured as the transmit pin, TXD0, of SCI0. While in reset and immediately out of reset the PS1 pin is configured as a high impedance input pin.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Modulator (PWM8B6CV1) Block Description” for information about pin configurations. PU[5:4] are not available in the 80 pin package version. 1.4.42 PU[3:0] / IOC2[7:4]/PW1[3:0] — Port U I/O Pins [3:0] PU[3:0] are general purpose input or output pins. When the Timer system 2 (TIM2) is enabled they can also be configured as the TIM2 input capture or output compare pins IOC2[7-4].
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-5. MC9S12E256 Power and Ground Connection Summary Mnemonic Nominal Voltage VDD1, VDD2 2.5 V VSS1, VSS2 0V VDDR 3.3/5.0 V VSSR 0V VDDX 3.3/5.0 V VSSX 0V VDDA 3.3/5.0 V VSSA 0V VRH 3.3/5.0 V VRL 0V VDDPLL 2.5 V VSSPLL 0V Description Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.5 System Clock Description The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 1-7 shows the clock connections from the CRG to all modules. Consult Chapter 4, “Clocks and Reset Generator (CRGV4) Block Description” for details on clock generation.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.6 Modes of Operation 1.6.1 Overview Eight possible modes determine the operating configuration of the MC9S12E256. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device. 1.6.2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.7 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • Protection of the contents of FLASH, • Operation in single-chip mode, • Operation from external memory with internal FLASH disabled. The user must be reminded that part of the security must lie with the user’s code.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 1.8 Low Power Modes The microcontroller features three main low power modes. Consult the respective block description chapter for information on the module behavior in Stop, Pseudo Stop, and Wait Mode.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-9.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) Table 1-9.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) 1.9.2.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module block description chapters for register reset states. Refer to Chapter 18, “Multiplexed External Bus Interface (MEBIV3)” for mode dependent pin configuration of port A, B and E out of reset.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) NOTE: Oscillator in Colpitts mode. C1 VDD1 VSSA VSS1 C3 VDDA VDDX VSS2 C2 C6 VDD2 VSSX VSSR C4 C7 C8 C10 C9 R1 C11 C5 VDDR Q1 VSSPLL VDDPLL Figure 1-8. Recommended PCB Layout (112-LQFP) MC9S12E256 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) NOTE: Oscillator in Colpitts mode. VSSA C1 VDD1 C3 VSS1 VDDA VSS2 VDDX C2 C6 VDD2 VSSX VSSR C4 C7 C8 C11 C5 VDDR C10 C9 Q1 VSSPLL R1 VDDPLL Figure 1-9. Recommended PCB Layout (80-QFP) MC9S12E256 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1) MC9S12E256 Data Sheet, Rev. 1.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Table 2-1. FTS256K2 Revision History Version Number Revision Date V01.01 04APR05 V01.02 15SEP06 1. 2. 3. Add address range restriction to data compress command. Describe algorithm for data compress command. Add note about margin read during data compress command. V01.03 05DEC06 1. Clarify in Section 2.3.2.7,Section 2.4.1.2, Section 2.4.1.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.1.2 • • • • • • • • • • 2.1.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) FTS256K2 Command Interface Common Registers Banked Registers Command Interrupt Request Flash Block 0 64K * 16 Bits sector 0 sector 1 Command Pipelines Flash Block 0-1 comm2 addr2 data2 comm1 addr1 data1 sector 127 Flash Block 1 64K * 16 Bits Protection sector 0 sector 1 sector 127 Security Oscillator Clock Clock Divider FCLK Figure 2-1. FTS256K2 Block Diagram 2.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.3.1 Module Memory Map The Flash memory map is shown in Figure 2-2. The HCS12 architecture places the Flash memory addresses between 0x4000 and 0xFFFF which corresponds to three 16-Kbyte pages. The content of the HCS12 core PPAGE register is used to map the logical middle page ranging from address 0x8000 to 0xBFFF to any physical 16 Kbyte page in the Flash memory.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) (16 bytes) MODULE BASE + 0x0000 Flash Registers MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E 0x8000 Flash Blocks 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Block 0 0xC000 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 Block 1 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00 – 0xFF0F, Flash Configurati
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Table 2-3. Detailed Flash Memory Map MCU Address Range 0x4000–0x7FFF PPAGE Unpaged (0x3E) Protectable Lower Range Protectable Higher Range Flash Block Block Relative Address1 0x4000–0x43FF N.A. 0 0x018000–0x01BFFF 1 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x30 N.A. N.A. 0x31 N.A. N.A. 0x004000–0x007FFF 0x000000–0x003FFF 0x32 N.A. N.A. 0x008000–0x00BFFF 0x33 N.A. N.A. 0x00C000–0x00FFFF 0x34 N.A. N.A.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) The Flash module also contains a set of 16 control and status registers located in address space module base + 0x0000 to module base + 0x000F. In order to accommodate more than one Flash block with a minimum register address space, a set of registers located from module base + 0x0004 to module base + 0x000B are repeated in all banks. The active register bank is selected by the BKSEL bits in the unbanked Flash configuration register (FCNFG).
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.3.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Register Name 0x000D RESERVED2 0x000E RESERVED3 0x000F RESERVED4 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W = Unimplemented or Reserved Figure 2-3. FTS256K2 Register Summary (continued) 2.3.2.1 Flash Clock Divider Register (FCLKDIV) The unbanked FCLKDIV register is used to control timed events in program and erase algorithms.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.3.2.2 Flash Security Register (FSEC) The unbanked FSEC register holds all bits associated with the security of the MCU and Flash module. Module Base + 0x0001 7 R 6 KEYEN 5 4 3 2 RNV5 RNV4 RNV3 RNV2 F F F F 1 0 SEC W Reset F F F F = Unimplemented or Reserved Figure 2-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) The security function in the Flash module is described in Section 2.6, “Flash Module Security”. 2.3.2.3 Flash Test Mode Register (FTSTMOD) The unbanked FTSTMOD register is used to control Flash test features. Module Base + 0x0002 R 7 6 5 0 0 0 4 3 2 1 0 0 0 0 0 0 0 0 0 WRALL W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-6. Flash Test Mode Register (FTSTMOD) All bits read 0 and are not writable in normal mode.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Table 2-10. FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 2.3.2.7, “Flash Status Register (FSTAT)”) is set.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Trying to alter data in any of the protected areas in the Flash block will result in a protection violation error and the PVIOL flag will be set in the FSTAT register. A mass erase of the Flash block is not possible if any of the contained Flash sectors are protected. Table 2-12. FPROT Field Descriptions Field Description 7 FPOPEN Protection Function Bit — The FPOPEN bit determines the protection function for program or erase as shown in Table 2-13.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Table 2-14. Flash Protection Higher Address Range FPHS[1:0] Unpaged Address Range Paged Address Range Protected Size 00 0xF800–0xFFFF 0x0037/0x003F: 0xC800–0xCFFF 2 Kbytes 01 0xF000–0xFFFF 0x0037/0x003F: 0xC000–0xCFFF 4 Kbytes 10 0xE000–0xFFFF 0x0037/0x003F: 0xB000–0xCFFF 8 Kbytes 11 0xC000–0xFFFF 0x0037/0x003F: 0x8000–0xCFFF 16 Kbytes Table 2-15.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Scenario FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPOPEN = 1 FPLS[1:0] PPAGE 0x0030–0x0035 0x0038–0x003D Scenario FPHS[1:0] PPAGE 0x0036–0x0037 0x003E–0x003F FPHS[1:0] PPAGE 0x0036–0x0037 0x003E–0x003F FPOPEN = 0 FPLS[1:0] PPAGE 0x0030–0x0035 0x0038–0x003D Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions. Table 2-16. Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 2 3 0 X X X X 1 X 2 X 4 X X X X X X X X X X 7 2.3.2.7 X X 6 7 X 3 6 5 X X 5 1 4 X X X X X X Allowed transitions marked with X.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in the current banked FSTAT register when starting a command write sequence. Table 2-17.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.3.2.8 Flash Command Register (FCMD) The banked FCMD register is the Flash command register. Module Base + 0x0006 7 R 6 5 4 3 0 0 1 0 0 0 0 CMDB W Reset 2 0 0 0 0 = Unimplemented or Reserved Figure 2-12. Flash Command Register (FCMD - NVM User Mode) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 2-18.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Table 2-20. FCTL Field Descriptions Field Description 7-0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 2.3.2.10 Flash Address Registers (FADDR) The banked FADDRHI and FADDRLO registers are the Flash address registers. Module Base + 0x0008 7 6 5 4 R 3 2 1 0 0 0 0 0 FADDRHI W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-14.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Module Base + 0x000B 7 6 5 4 R 3 2 1 0 0 0 0 0 FDATALO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 2-17. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. After an array write as part of a command write sequence, the FDATA registers will contain the data written. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.3.2.14 RESERVED3 This register is reserved for factory testing and is not accessible. Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-20. RESERVED3 All bits read 0 and are not writable. 2.3.2.15 RESERVED4 This register is reserved for factory testing and is not accessible.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) The next paragraphs describe: 1. How to write the FCLKDIV register. 2. Command write sequences used to program, erase, and verify the Flash memory. 3. Valid Flash commands. 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations. 2.4.1.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) START Tbus < 1µs? NO ALL COMMANDS IMPOSSIBLE YES PRDIV8=0 (reset) OSCILLATOR CLOCK > 12.8 MHZ? NO YES PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? YES PRDCLK=oscillator_clock NO FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, and data compress algorithms. Before starting a command write sequence, the ACCERR, PVIOL, and FAIL flags must be clear in all of the banked FSTAT registers (see Section 2.3.2.7, “Flash Status Register (FSTAT)”) and the CBEIF flag must be tested to determine the state of the address, data, and command buffers.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. After a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.3.1 Erase Verify Command The erase verify operation is used to confirm that a Flash block is erased. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a second command has been buffered.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.3.2 Data Compress Command The data compress command is used to check Flash code integrity by compressing data from a selected portion of the Flash block into a signature analyzer. The starting address for the data compress operation is defined by the address written during the command write sequence. The number of consecutive word addresses compressed is defined by the data written during the command write sequence.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Read: Register FCLKDIV Clock Register Loaded Check Bit FDIVLD set? yes no Write: Register FCLKDIV 1. Write: Flash address to start compression and number of word addresses to compress (max 16,384) 2. Write: Register FCMD Data Compress Command 0x06 NOTE: command write sequence aborted by writing 0x00 to FSTAT register. 3. Write: Register FSTAT Clear bit CBEIF 0x80 NOTE: command write sequence aborted by writing 0x00 to FSTAT register.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature based on selected Flash array data. The final signature, which is stored in the associated banked FDATA register, is based on the following logic equation which is executed on every data compression cycle during the operation: MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.3.3 Program Command The program command is used to program a previously erased word in the Flash memory using an embedded algorithm. If the word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.3.4 Sector Erase Command The sector erase command is used to erase the addressed sector in the Flash memory using an embedded algorithm. If the Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.3.5 Mass Erase Command The mass erase command is used to erase a Flash memory block using an embedded algorithm. If the Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. After the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a second command has been buffered.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.3.6 Sector Erase Abort Command The sector erase abort command is used to terminate the sector erase operation so that other sectors in the Flash block are available for read and program operations without waiting for the sector erase operation to complete.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Execute Sector Erase Command Flow Bit Polling for Command Completion Check Bit CCIF Set? Erase Abort Needed? no yes no Read: Register FSTAT yes EXIT 1. Write: Dummy Flash Address and Dummy Data NOTE: command write sequence aborted by writing 0x00 to 2. FSTAT register. Write: Register FCMD Sector Erase Abort Cmd 0x47 NOTE: command write sequence aborted by writing 0x00 to 3. FSTAT register.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.4.1.4 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing to a Flash address in the range 0x8000–0xBFFF when the PPAGE register does not select a 16 Kbyte page in the Flash block selected by the BKSEL bit in the FCNFG register. 3.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 3. Writing the mass erase command while any Flash protection is enabled. If the PVIOL flag is set in any of the banked FSTAT registers, the user must clear the PVIOL flag in all of the banked FSTAT registers before starting another command write sequence (see Section 2.3.2.7, “Flash Status Register (FSTAT)”). 2.5 2.5.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) 2.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0xFF00–0xFF07). If the KEYEN[1:0] bits are in the enabled state (see Section 2.3.2.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) is determined by the Flash security byte (0xFF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single-chip mode by using the backdoor key access sequence via the background debug mode (BDM). 2.6.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) Table 2-22. Flash Interrupt Sources Interrupt Source Interrupt Flag Flash address, data and command buffers empty All Flash commands completed Local Enable Global (CCR) Mask CBEIF (FSTAT register) CBEIE (FCNFG register) CCIF (FSTAT register) CCIE (FCNFG register) I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 2.8.
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Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1) MC9S12E256 Data Sheet, Rev. 1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.1 lntroduction The port integration module establishes the interface between the peripheral modules and the I/O pins for for ports AD, M, P, Q, S, T and U.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.1.2 Block Diagram Figure 3-1 is a block diagram of the PIM9E256V1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.2 External Signal Description This section lists and describes the signals that connect off chip. Table 3-1 shows all the pins and their functions that are controlled by the PIM9E256V1. The order in which the pin functions are listed represents the functions priority (top – highest priority, bottom – lowest priority). Table 3-1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3 Memory Map and Register Definition This section provides a detailed description of all registers. Table 3-2 is a standard memory map of port integration module. Table 3-2.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-2.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Refer to the ATD block description chapter for information on the ATDDIEN0 and ATDDIEN1 registers. During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is disabled). 3.3.1.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.2 Port AD Input Register (PTIAD) Module Base + 0x0032 R 7 6 5 4 3 2 1 0 PTIAD15 PTIAD14 PTIAD13 PTIAD12 PTIAD11 PTIAD10 PTIAD9 PTIAD8 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIAD0 1 1 1 1 1 1 1 1 W Reset Module Base + 0x0033 R W Reset = Reserved or Unimplemented Figure 3-3. Port AD Input Register (PTIAD) Read: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.3 Port AD Data Direction Register (DDRAD) Module Base + 0x0034 7 6 5 4 3 2 1 0 DDRAD15 DDRAD14 DDRAD13 DDRAD12 DDRAD11 DDRAD10 DDRAD9 DDRAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 0 0 0 0 0 0 0 0 R W Reset Module Base + 0x0035 R W Reset Figure 3-4. Port AD Data Direction Register (DDRAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.4 Port AD Reduced Drive Register (RDRAD) Module Base + 0x0036 7 6 5 4 3 2 1 0 RDRAD15 RDRAD14 RDRAD13 RDRAD12 RDRAD11 RDRAD10 RDRAD9 RDRAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 0 0 0 0 0 0 0 0 R W Reset Module Base + 0x0037 R W Reset Figure 3-5. Port AD Reduced Drive Register (RDRAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.5 Port AD Pull Device Enable Register (PERAD) Module Base + 0x0038 7 6 5 4 3 2 1 0 PERAD15 PERAD14 PERAD13 PERAD12 PERAD11 PERAD10 PERAD9 PERAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 0 0 0 0 0 0 0 0 R W Reset Module Base + 0x0039 R W Reset Figure 3-6. Port AD Pull Device Enable Register (PERAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.6 Port AD Polarity Select Register (PPSAD) Module Base + 0x003A 7 6 5 4 3 2 1 0 PPSAD15 PPSAD14 PPSAD13 PPSAD12 PPSAD11 PPSAD10 PPSAD9 PPSAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 0 0 0 0 0 0 0 0 R W Reset Module Base + 0x003B R W Reset Figure 3-7. Port AD Polarity Select Register (PPSAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.7 Port AD Interrupt Enable Register (PIEAD) Module Base + 0x003C 7 6 5 4 3 2 1 0 PIEAD15 PIEAD14 PIEAD13 PIEAD12 PIEAD11 PIEAD10 PIEAD9 PIEAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PIEAD7 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 PIEAD0 0 0 0 0 0 0 0 0 R W Reset Module Base + 0x003D R W Reset Figure 3-8. Port AD Interrupt Enable Register (PIEAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.1.8 Port AD Interrupt Flag Register (PIFAD) Module Base + 0x003E 7 6 5 4 3 2 1 0 PIFAD15 PIFAD14 PIFAD13 PIFAD12 PIFAD11 PIFAD10 PIFAD9 PIFAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PIFAD7 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0 0 0 0 0 0 0 0 0 R W Reset Module Base + 0x003F R W Reset Figure 3-9. Port AD Interrupt Flag Register (PIFAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.2 Port M Port M is associated with the serial communication interface (SCI2) , Inter-IC bus (IIC) and the digital to analog converter (DAC0 and DAC1) modules. Each pin is assigned to these modules according to the following priority: IIC/SCI2/DAC1/DAC0 > general-purpose I/O. When the IIC bus is enabled, the PM[7:6] pins become SCL and SDA respectively.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.2.2 Port M Input Register (PTIM) Module Base + 0x0011 R 7 6 5 4 3 2 1 0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 0 PTIM1 PTIM0 u u u u u 0 u u 1 0 DDRM1 DDRM0 0 0 W Reset = Reserved or Unimplemented u = Unaffected by reset Figure 3-11. Port M Input Register (PTIM) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. 3.3.2.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-9. DDRM Field Descriptions Field 7:3, 1:0 DDRM[7:3, 1:0] 3.3.2.4 Description Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Port M Reduced Drive Register (RDRM) Module Base + 0x0013 7 6 5 4 3 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 0 0 0 0 0 R 2 1 0 RDRM1 RDRM0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-13.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.2.5 Port M Pull Device Enable Register (PERM) Module Base + 0x0014 7 6 5 4 3 PERM7 PERM6 PERM5 PERM4 PERM3 0 0 0 0 0 R 2 1 0 PERM1 PERM0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-14. Port M Pull Device Enable Register (PERM) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description Table 3-12. PPSM Field Descriptions Field 7:3, 1:0 PPSM[7:3, 1:0] 3.3.2.7 Description Pull Select Port M 0 A pull-up device is connected to the associated port M pin. 1 A pull-down device is connected to the associated port M pin. Port M Wired-OR Mode Register (WOMM) Module Base + 0x0016 7 6 5 4 WOMM7 WOMM6 WOMM5 WOMM4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset = Reserved or Unimplemented Figure 3-16.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.3 Port P Port P is associated with the Pulse Width Modulator (PMF) modules. Each pin is assigned according to the following priority: PMF > general-purpose I/O. When a PMF channel is enabled, the corresponding pin becomes a PWM output. Refer to the PMF block description chapter for information on enabling and disabling the PWM channels. During reset, port P pins are configured as high-impedance inputs. 3.3.3.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.3.3 Port P Data Direction Register (DDRP) Module Base + 0x001A R 7 6 0 0 5 4 3 2 1 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 W Reset 0 0 = Reserved or Unimplemented Figure 3-19. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures port pins PP[5:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.3.5 Port P Pull Device Enable Register (PERP) Module Base + 0x001C R 7 6 0 0 5 4 3 2 1 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 W Reset 0 0 = Reserved or Unimplemented Figure 3-21. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.4 Port Q Port Q is associated with the Pulse Width Modulator (PMF) modules. Each pin is assigned according to the following priority: PMF > general-purpose I/O. When a current status or fault function is enabled, the corresponding pin becomes an input. PQ[3:0] are connected to FAULT[3:0] inputs and PQ[6:4] are connected to IS[2:0] inputs of the PMF module.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.4.3 Port Q Data Direction Register (DDRQ) Module Base + 0x0022 7 R 6 5 4 3 2 1 0 DDRQ6 DDRQ5 DDRQ4 DDRQ3 DDRQ2 DDRQ1 DDRQ0 0 0 0 0 0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-25. Port Q Data Direction Register (DDRQ) Read: Anytime. Write: Anytime. This register configures port pins PQ[6:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.4.5 Port Q Pull Device Enable Register (PERQ) Module Base + 0x0024 7 R 6 5 4 3 2 1 0 PERQ6 PERQ5 PERQ4 PERQ3 PERQ2 PERQ1 PERQ0 0 0 0 0 0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-27. Port Q Pull Device Enable Register (PERQ) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.5 Port S Port S is associated with the serial peripheral interface (SPI) and serial communication interfaces (SCI0 and SCI1). Each pin is assigned to these modules according to the following priority: SPI/SCI1/SCI0 > general-purpose I/O. When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the SPI block description chapter for information on enabling and disabling the SPI.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description This register always reads back the status of the associated pins. 3.3.5.3 Port S Data Direction Register (DDRS) Module Base + 0x000A 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 3-31. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures port pins PS[7:4] and PS[2:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.5.4 Port S Reduced Drive Register (RDRS) Module Base + 0x000B 7 6 5 4 3 2 1 0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 3-32. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.5.6 Port S Polarity Select Register (PPSS) Module Base + 0x000D 7 6 5 4 3 2 1 0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 R W Reset Figure 3-34. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. The Port S Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.6 Port T Port T is associated with two 4-channel timers (TIM0 and TIM1). Each pin is assigned to these modules according to the following priority: TIM1/TIM0 > general-purpose I/O. If the timer TIM0 is enabled, the channels configured for output compare are available on port T pins PT[3:0]. If the timer TIM1 is enabled, the channels configured for output compare are available on port T pins PT[7:4].
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.6.3 Port T Data Direction Register (DDRT) Module Base + 0x0002 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 3-38. Port T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures port pins PT[7:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.6.5 Port T Pull Device Enable Register (PERT) Module Base + 0x0004 7 6 5 4 3 2 1 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0 0 0 0 0 0 0 0 R W Reset Figure 3-40. Port T Pull Device Enable Register (PERT) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.7 Port U Port U is associated with one 4-channel timer (TIM2) and the pulse width modulator (PWM) module. Each pin is assigned to these modules according to the following priority: TIM2/PWM > general-purpose I/O. If the timer TIM2 is enabled, the channels configured for output compare are available on port U pins PU[3:0]. Refer to the TIM block description chapter for information on enabling and disabling the TIM module.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description This register always reads back the status of the associated pins. 3.3.7.3 Port U Data Direction Register (DDRU) Module Base + 0x002A 7 6 5 4 3 2 1 0 DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0 0 0 0 0 0 0 0 0 R W Reset Figure 3-44. Port U Data Direction Register (DDRU) Read: Anytime. Write: Anytime. This register configures port pins PU[7:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.7.4 Port U Reduced Drive Register (RDRU) Module Base + 0x002B 7 6 5 4 3 2 1 0 RDRU7 RDRU6 RDRU5 RDRU4 RDRU3 RDRU2 RDRU1 RDRU0 0 0 0 0 0 0 0 0 R W Reset Figure 3-45. Port U Reduced Drive Register (RDRU) Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.3.7.6 Port U Polarity Select Register (PPSU) Module Base + 0x002D 7 6 5 4 3 2 1 0 PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0 0 0 0 0 0 0 0 0 R W Reset Figure 3-47. Port U Polarity Select Register (PPSU) Read: Anytime. Write: Anytime. The Port U Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.4 Functional Description Each pin associated with ports AD, M, P, Q, S, T and U can act as general-purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description PTIx 0 1 PTx PAD 0 1 DDRx 0 1 Digital Module data out output enable module enable Figure 3-49. Illustration of I/O Pin Functionality Figure 3-50 shows the state of digital inputs and outputs when an analog module drives the port. When the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read “1”.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.4.6 Polarity Select Register The Polarity Select Register selects either a pull-up or pull-down device if enabled. The pull device becomes active only if the pin is used as an input or as a wired-or output. 3.4.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.5 Resets The reset values of all registers are given in the register description in Section 3.3, “Memory Map and Register Definition”. All ports start up as general-purpose inputs on reset. 3.5.1 Reset Initialization All registers including the data registers get set/reset asynchronously. Table 3-37 summarizes the port properties after reset initialization. P Table 3-37.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description 3.6 3.6.1 Interrupts General Port AD generates an edge sensitive interrupt if enabled. It offers sixteen I/O pins with edge triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector.
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Chapter 3 Port Integration Module (PIM9E256V1) Block Description tpulse Figure 3-52. Pulse Illustration A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the port integration module.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.1 Introduction This specification describes the function of the clocks and reset generator (CRGV4). 4.1.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Voltage Regulator Power-on Reset Low Voltage Reset 1 CRG RESET CM fail Clock Monitor OSCCLK EXTAL Oscillator XTAL COP Timeout XCLKS Reset Generator Clock Quality Checker COP RTI System Reset Bus Clock Core Clock Oscillator Clock Registers XFC VDDPLL VSSPLL PLLCLK PLL Clock and Reset Control Real-Time Interrupt PLL Lock Interrupt Self-Clock Mode Interrupt 1 Refer to the device overview section for availability of the low-volta
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description VDDPLL CS CP MCU RS XFC Figure 4-2. PLL Loop Filter Connections 4.2.3 RESET — Reset Pin RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. 4.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the CRGV4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level. 4.3.2 Register Descriptions This section describes in address order all the CRGV4 registers and their individual bits.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Register Name 0x000B ARMCOP Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = Unimplemented or Reserved Figure 4-3. CRG Register Summary (continued) 4.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.3.2.2 CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1. Module Base + 0x0001 R 7 6 5 4 0 0 0 0 3 2 1 0 REFDV3 REFDV2 REFDV1 REFDV0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 4-5.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.3.2.4 CRG Flags Register (CRGFLG) This register provides CRG status bits and flags. Module Base + 0x0003 7 6 5 4 RTIF PORF LVRF LOCKIF 0 Note 1 Note 2 0 R 3 2 LOCK TRACK 1 0 SCM SCMIF W Reset 0 0 0 0 1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved Figure 4-7.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-2. CRGFLG Field Descriptions (continued) Field 1 SCMIF 0 SCM 4.3.2.5 Description Self-Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self-Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 4-17 for details on the effect of each bit. Module Base + 0x0005 7 6 5 4 3 2 1 0 PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI 0 0 0 0 0 0 0 0 R W Reset Figure 4-9. CRG Clock Select Register (CLKSEL) Read: anytime Write: refer to each bit for individual write conditions Table 4-4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-4. CLKSEL Field Descriptions (continued) Field 2 CWAI Description Core Stops in Wait Mode Bit — Write: anytime 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. 1 RTIWAI RTI Stops in Wait Mode Bit — Write: anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-5. PLLCTL Field Descriptions (continued) Field Description 5 AUTO Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-6. RTICTL Field Descriptions Field Description 6:4 RTR[6:4] Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 4-7. 3:0 RTR[3:0] Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity. Table 4-7 shows all possible divide values selectable by the RTICTL register.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. Module Base + 0x0008 7 6 WCOP RSBCK 0 0 R 5 4 3 0 0 0 2 1 0 CR2 CR1 CR0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 4-12. CRG COP Control Register (COPCTL) Read: anytime Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode Write: RSBCK: once Table 4-8.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-13.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 4-15. ARMCOP Register Diagram Read: always reads 0x0000 Write: anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency fSCM.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. CORE CLOCK: BUS CLOCK / ECLK Figure 4-18. Core Clock and Bus Clock Relationship 4.4.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description check window 1 VCO clock 2 50000 49999 3 1 2 3 4 5 4096 OSCCLK 4095 osc ok Figure 4-19. Check Window Example The sequence for clock quality check is shown in Figure 4-20. CM fail Clock OK POR LVR exit full stop Clock Monitor Reset Enter SCM yes check window SCM active? num=num+1 yes osc ok num=50 no num=0 no ? num<50 ? yes no SCME=1 ? no yes SCM active? yes Switch to OSCCLK no Exit SCM Figure 4-20.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description NOTE The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo-stop mode or wait mode 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.4.6 Real-Time Interrupt (RTI) The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK (see Section Figure 4-22., “Clock Chain for RTI”). At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description running at minimum operating frequency; this mode of operation is called self-clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. See Section 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Core req’s Wait Mode. PLLWAI=1 ? no yes Clear PLLSEL, Disable PLL CWAI or SYSWAI=1 ? no yes Disable core clocks SYSWAI=1 ? no yes Disable system clocks no Enter Wait Mode CME=1 ? Wait Mode left due to external reset no yes Exit Wait w. ext.RESET CM fail ? INT ? yes no yes Exit Wait w.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description There are five different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Self-clock mode interrupt • Real-time interrupt (RTI) If the MCU gets an external reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-11. Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 1 1 0 Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. – MCU remains in Wait Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-11. Outcome of Clock Loss in Wait Mode (continued) CME SCME SCMIE 1 1 1 CRG Actions Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Core req’s Stop Mode. Clear PLLSEL, Disable PLL Exit Stop w. ext.RESET no Wait Mode left due to external INT ? no Enter Stop Mode PSTP=1 ? yes CME=1 ? yes no Exit Stop w. CMRESET no SCME=1 ? no yes Clock OK ? CM fail ? INT ? no yes no yes yes Exit Stop w.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and the MCU is in run mode again.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-12. Outcome of Clock Loss in Pseudo-Stop Mode CME SCME SCMIE CRG Actions 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 1 1 0 Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Table 4-12. Outcome of Clock Loss in Pseudo-Stop Mode (continued) CME SCME SCMIE 1 1 1 CRG Actions Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. 4.4.10.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description Definition.” All reset sources are listed in Table 4-13. Refer to the device overview chapter for related vector addresses and priorities. Table 4-13.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector. 4.5.
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Chapter 4 Clocks and Reset Generator (CRGV4) Block Description 4.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 4-15. Refer to the device overview chapter for related vector addresses and priorities. Table 4-15. CRG Interrupt Vectors 4.6.
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Chapter 5 Oscillator (OSCV2) Block Description 5.1 Introduction The OSCV2 module provides two alternative oscillator concepts: • A low noise and low power Colpitts oscillator with amplitude limitation control (ALC) • A robust full swing Pierce oscillator with the possibility to feed in an external square wave 5.1.
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Chapter 5 Oscillator (OSCV2) Block Description 5.2 External Signal Description This section lists and describes the signals that connect off chip. 5.2.1 VDDPLL and VSSPLL — PLL Operating Voltage, PLL Ground These pins provide the operating voltage (VDDPLL) and ground (VSSPLL) for the OSCV2 circuitry. This allows the supply voltage to the OSCV2 to be independently bypassed. 5.2.
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Chapter 5 Oscillator (OSCV2) Block Description EXTAL MCU RB C3 Crystal or Ceramic Resonator RS* XTAL C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. Figure 5-2. Pierce Oscillator Connections (XCLKS = 1) EXTAL CMOS-Compatible External Oscillator (VDDPLL Level) MCU XTAL Not Connected Figure 5-3. External Clock Connections (XCLKS = 1) 5.2.
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Chapter 5 Oscillator (OSCV2) Block Description 5.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the OSCV2 module. 5.4 Functional Description The OSCV2 block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.1 Introduction The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy. 6.1.1 • • • • • • • • • • • • • • 6.1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Bus Clock ATD clock Clock Prescaler Trigger Mux ETRIG0 ETRIG1 ETRIG2 ATD10B16C Sequence Complete Mode and Timing Control Interrupt ETRIG3 (see Device Overview chapter for availability and connectivity) ATDDIEN ATDCTL1 Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 PORTAD VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL AN15 AN14 AN13 AN12 AN11
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.2 External Signal Description This section lists all inputs to the ATD10B16C block. 6.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion. 6.2.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description . Table 6-1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2 Register Descriptions This section describes in address order all the ATD10B16C registers and their individual bits.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Register Name 0x000D ATDDIEN1 R W 0x000E PORTAD0 R Bit 7 6 5 4 3 2 1 Bit 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W 0x000F PORTAD1 R W R BIT 9 MSB BIT 7 MSB 0x0010–0x002
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-3. Multi-Channel Wrap Around Coding 6.3.2.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-5. External Trigger Channel Select Coding 1 6.3.2.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Module Base + 0x0002 7 6 5 4 3 2 1 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 R 0 ASCIF W Reset 0 = Unimplemented or Reserved Figure 6-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 6-6. ATDCTL2 Field Descriptions Field Description 7 ADPU ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-6. ATDCTL2 Field Descriptions (continued) Field Description 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 6.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0003 7 R 6 5 4 3 2 1 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 1 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 6-6.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-8. ATDCTL3 Field Descriptions (continued) Field Description 2 FIFO Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-10. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately MC9S12E256 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-13. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock1 Min.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-14. ATDCTL5 Field Descriptions (continued) Field Description 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 6-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-17. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 MC9S12E256 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 6 R 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 6-9.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-18. ATDSTAT0 Field Descriptions (continued) Field Description 4 FIFOR FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.8 Reserved Register 0 (ATDTEST0) Module Base + 0x0008 R 7 6 5 4 3 2 1 0 u u u u u u u u 1 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved u = Unaffected Figure 6-10. Reserved Register 0 (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 6.3.2.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-20. Special Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 X X Reserved 6.3.2.10 1 0 1 0 0 VRH 1 0 1 0 1 VRL 1 0 1 1 0 (VRH+VRL) / 2 1 0 1 1 1 Reserved 1 1 X X X Reserved ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.11 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags CCF7 to CCF0 Module Base + 0x000B R 7 6 5 4 3 2 1 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 6-13. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 6-22.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.12 ATD Input Enable Register 0 (ATDDIEN0) Module Base + 0x000C 7 6 5 4 3 2 1 0 IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 0 0 0 0 0 0 0 0 R W Reset Figure 6-14. ATD Input Enable Register 0 (ATDDIEN0) Read: Anytime Write: anytime Table 6-23.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.14 Port Data Register 0 (PORTAD0) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. Module Base + 0x000E R 7 6 5 4 3 2 1 0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 1 1 1 1 1 1 1 1 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 W Reset Pin Function = Unimplemented or Reserved Figure 6-16.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.15 Port Data Register 1 (PORTAD1) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. Module Base + 0x000F R 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 1 1 1 1 1 1 1 AN 7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 W Reset Pin Function = Unimplemented or Reserved Figure 6-17.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.16 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.3.2.16.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA. 6.4.1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 6-27. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Falling edge triggered. Performs one conversion sequence per trigger. 0 1 1 X Rising edge triggered. Performs one conversion sequence per trigger.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description • Entering wait mode, the ATD conversion either continues or halts for low power depending on the logical value of the AWAIT bit. Freeze Mode Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.5.1.5 Step 5 Configure starting channel, single/multiple channel, continuous or single sequence and result data format in ATDCTL5. Writing ATDCTL5 will start the conversion, so make sure your write ATDCTL5 in the last step. Example: Leave CD, CC,CB,CA clear to start on channel AN0. Write MULT=1 to convert channel AN0 to AN3 in a sequence (4 conversion per sequence selected in ATDCTL3). 6.5.2 6.5.2.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description 6.7 Interrupts The interrupt requested by the ATD10B16C is listed in Table 6-28. Refer to MCU specification for related vector address and priority. Table 6-28. ATD Interrupt Vectors Interrupt Source Sequence Complete Interrupt CCR Mask Local Enable I bit ASCIE in ATDCTL2 See Section 6.3.2, “Register Descriptions,” for further details. MC9S12E256 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.1 Introduction The DAC8B1C is a 8-bit, 1-channel digital-to-analog converter module. 7.1.1 Features The DAC8B1C includes these features: • 8-bit resolution. • One output independent monotonic channel. 7.1.2 Modes of Operation The DAC8B1C functions the same in normal, special, and emulation modes. It has two low-power modes, wait and stop modes. 7.1.2.1 Run Mode Normal mode of operation. 7.1.2.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description CONTROL CIRCUIT DAC CHANNEL VRL DACD DACC VREF VDDA VSSA O/P VOLTAGE DAO ANALOG SUB-BLOCK Figure 7-1. DAC8B1C Functional Block Diagram 7.2 Signal Description The DAC8B1C module requires four external pins. These pins are listed in Table 7-1 below. Table 7-1.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.2.1 DAO — DAC Channel Output This pin is used as the analog output pin of the DAC8B1C module. The value represents the analog voltage level between VSSA and VREF. 7.2.2 VDDA — DAC Power Supply This pin serves as the power supply pin.l 7.2.3 VSSA — DAC Ground Supply This pin serves as an analog ground reference to the DAC. 7.2.4 VREF — DAC Reference Supply This pin serves as the source for the high reference potential.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.3.2 Register Descriptions This section consists of register descriptions arranged in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in descending bit order. 7.3.2.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.3.2.2 Reserved Register (DACC1) This register is reserved. Module Base + 0x0000 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-4. Reserved Register (DACC1) Read: always read $00 Write: unimplemented 7.3.2.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.3.2.4 DAC Data Register — Right Justified (DACD) Module Base + 0x0003 7 6 5 4 3 2 1 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 0 0 R W Reset Figure 7-6. DAC Data Register — Right Justified (DACD) Read: read zeroes when DJM is clear Write: unimplemented when DJM is clear The DAC data register is an 8-bit readable/writable register that stores the data to be converted when DJM bit is set.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description 7.4 Functional Description The DAC8B1C module consists of analog and digital sub-blocks. 7.4.1 Functional Description Data to be converted is written to DACD register. The data can be mapped either to left end or right end of DACD register by clearing or setting DJM bit of DACC0 register. Also, the data written to DACD can be a signed or unsigned data depending on DSGN bit of DACC0 register. See Table 7-3 below for data formats.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Block Description Conversion of the data in DACD register takes place as soon as DACE bit of DACC0 is set. The transfer characteristic of the day module is shown in Figure 7-7. 256 LSB Analog Output Voltage 255 LSB 3 LSB 2 LSB $FF $FE $02 $00 $01 1 LSB Digital Input 1 LSB = 21.5 mV when VDDA = 5.5 V 1 LSB = 11.5 mV when VDDA = 3.0 V Figure 7-7. DAC8B1C Transfer Function 7.5 7.5.1 Resets General The DAC8B1C module is reset on a system reset.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.1 Revision History Table 8-1. SCI Revision History Version Number Revision Date 04.00 07/30/2002 04.02 04/16/2004 8.2 Effective Date Author Description of Changes Add two polarity configure bits to control the polarity of transmit data and receive data respectively; Add 1/4 pulse width option for TNP[1:0]=11 in SCIBDRH register. Update OR flag and PF flag description; Correct baud rate tolerance in 4.6.5.1 and 4.6.5.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description TXD: transmit pin 8.2.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.2.3.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description SCI Data Register IDLE Interrupt Request RXD Data In Infrared Decoder Receive Shift Register IRQ Generation Receive & Wakeup Control Bus Clk BAUD Generator ÷16 RDRF/OR Interrupt Request Data Format Control TDRE Interrupt Request SCI Interrupt Request Transmit Control Transmit Shift Register IRQ Generation TC Interrupt Request SCI Data Register Infrared Data Out TXD Encoder Figure 8-1.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.3 External Signal Descriptions The SCI module has a total of two external pins. 8.3.1 TXD — SCI Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 8.3.2 RXD — SCI Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description Register Name 0x0003 SCICR2 0x0004 SCISR1 0x0005 SCISR2 0x0006 SCIDRH 0x0007 SCIDRL Bit 7 6 5 4 3 2 1 Bit 0 TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R W R W R RAF W R R8 T8 W R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 = Unimplemented or Reserved Figure 8-2. SCI Registers Summary MC9S12E256 Data Sheet, Rev. 1.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.4.2.1 SCI Baud Rate Registers (SCIBDH and SCIBDL) Module Base + 0x0000 7 6 5 4 3 2 1 0 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 R W Reset Figure 8-3. SCI Baud Rate Register High (SCIBDH) Table 8-2. SCIBDH Field Descriptions Field 7 IREN 6:5 TNP[1:0] 4:0 SBR[11:8] Description Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description NOTE If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: anytime The SCI baud rate register is used to determine the baud rate of the SCI and to control the infrared modulation/demodulation submodule. Table 8-4.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description Table 8-5. SCICR1 Field Descriptions Field Description 7 LOOPS Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.4.2.3 SCI Control Register 2 (SCICR2) Module Base + 0x0003 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 R W Reset Figure 8-6. SCI Control Register 2 (SCICR2) Read: anytime Write: anytime Table 8-7. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit —TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.4.2.4 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provide inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description Table 8-8. SCISR1 Field Descriptions (continued) 1 2 Field Description 3 OR Overrun Flag2 — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.4.2.5 SCI Status Register 2 (SCISR2) Module Base + 0x0005 R 7 6 5 0 0 0 4 3 2 1 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 RAF W Reset 0 0 0 0 = Unimplemented or Reserved Figure 8-8. SCI Status Register 2 (SCISR2) Read: anytime Write: anytime Table 8-9. SCISR2 Field Descriptions Field Description 4 TXPOL Transmit Polarity — This bit control the polarity of the transmitted data.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.4.2.6 SCI Data Registers (SCIDRH and SCIDRL) Module Base + 0x0006 7 R 6 R8 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 T8 W Reset 0 0 = Unimplemented or Reserved Figure 8-9. SCI Data Register High (SCIDRH) Table 8-10. SCIDRH Field Descriptions Field Description 7 R8 Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
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Chapter 8 Serial Communication Interface (SCIV4) Block Description When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH) then to SCIDRL. 8.5 Functional Description This subsection provides a complete functional description of the SCI block, detailing the operation of the design from the end user’s perspective in a number of descriptions. Figure 8-11 shows the structure of the SCI module.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.5.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 kbits/s and 115.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8-BIT DATA FORMAT (BIT M IN SCICR1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 POSSIBLE PARITY BIT BIT 6 BIT 7 NEXT START BIT STOP BIT STANDARD SCI DATA INFRARED SCI DATA 9-BIT DATA FORMAT (BIT M IN SCICR1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 POSSIBLE PARITY BIT BIT 6 BIT 7 BIT 8 STOP BIT NEXT START BIT STANDARD SCI DATA INFRARED SCI DATA Figure 8-12.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.5.3 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR[12:0] bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.5.4 Transmitter INTERNAL BUS ÷ 16 BAUD DIVIDER STOP SBR12–SBR0 SCI DATA REGISTERS H 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 TXPOL SCTXD L PT PARITY GENERATION LOOP CONTROL BREAK (ALL 0s) PE PREAMBLE (ALL ONES) T8 SHIFT ENABLE LOAD FROM SCIDR MSB M START BUS CLOCK TO RECEIVER LOOPS RSRC TRANSMITTER CONTROL TDRE INTERRUPT REQUEST TC INTERRUPT REQUEST TDRE TE SBK TIE TC TCIE Figure 8-13.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description flag by writing another byte to the transmitter buffer (SCIDRH/SCIDRL), while the shift register is shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is 0. Writing to the SCIBDH has no effect without also writing to SCIBDL.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin 8.5.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 8.5.5.3 Data Sampling The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 8-16 summarizes the results of the data bit samples. Table 8-16. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description In Figure 8-16 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description In Figure 8-18, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description Figure 8-20 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.5.5.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.5.5.5.2 Fast Data Tolerance Figure 8-23 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but continues to be sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 8-23.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.5.5.6.1 Idle Input Line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
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Chapter 8 Serial Communication Interface (SCIV4) Block Description Table 8-18. SCI Interrupt Sources IDLE 8.6.1 SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle. Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description 8.6.2 Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. MC9S12E256 Data Sheet, Rev. 1.
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Chapter 8 Serial Communication Interface (SCIV4) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 9.1.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.1.3 Block Diagram Figure 9-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. 9.2.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description Table 9-2. SPICR1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. 6 SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.3.2.2 SPI Control Register 2 (SPICR2) Module Base 0x0001 R 7 6 5 0 0 0 4 3 MODFEN BIDIROE 0 0 2 1 0 SPISWAI SPC0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 9-4. SPI Control Register 2 (SPICR2) Read: anytime Write: anytime; writes to the reserved bits have no effect Table 9-4.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description Table 9-5. Bidirectional Pin Configurations (continued) Pin Mode SPC0 BIDIROE MISO MOSI Bidirectional 1 0 Slave In MOSI not used by SPI 1 Slave I/O 9.3.2.3 SPI Baud Rate Register (SPIBR) Module Base 0x0002 7 R 6 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 9-5.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description Table 9-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 MHz 0 0 0 0 0 1 4 6.25 MHz 0 0 0 0 1 0 8 3.125 MHz 0 0 0 0 1 1 16 1.5625 MHz 0 0 0 1 0 0 32 781.25 kHz 0 0 0 1 0 1 64 390.63 kHz 0 0 0 1 1 0 128 195.31 kHz 0 0 0 1 1 1 256 97.66 kHz 0 0 1 0 0 0 4 6.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description Table 9-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.21 kHz 1 0 1 1 0 1 384 65.10 kHz 1 0 1 1 1 0 768 32.55 kHz 1 0 1 1 1 1 1536 16.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.3.2.4 SPI Status Register (SPISR) Module Base 0x0003 R 7 6 5 4 3 2 1 0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 9-6. SPI Status Register (SPISR) Read: anytime Write: has no effect Table 9-8. SPISR Field Descriptions Field Description 7 SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description Write: anytime The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept new data.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI Data Register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. • SCK Clock In slave mode, SCK is the SPI clock input from the master. • MISO and MOSI Pins In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. • SS Pin The SS pin is the slave select input.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device, slave devices that are not selected do not interfere with SPI bus activities.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI Data Register should now be in the slave data register and the data that was in the slave data register should be in the master.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time. 9.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description End of Idle State Begin SCK Edge Nr.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) Figure 9-11. Baud Rate Divisor Equation 9.4.5 9.4.5.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.4.7 Operation in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. 9.4.8 Operation in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description 9.5 Reset The reset values of registers and signals are described in the Memory Map and Registers section (see Section 9.3, “Memory Map and Register Definition”) which details the registers and their bit-fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset.
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Chapter 9 Serial Peripheral Interface (SPIV3) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.1 Introduction The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 10.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 10-1. IIC Registers Start Stop Arbitration Control Clock Control In/Out Data Shift Register Interrupt bus_clock SCL SDA Address Compare Figure 10-1. IIC Block Diagram MC9S12E256 Data Sheet, Rev. 1.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.2 External Signal Description The IICV2 module has two external pins. 10.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 10.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 10.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-1. IBAD Field Descriptions Field Description 7:1 ADR[7:1] Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. 0 Reserved Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0. 10.3.2.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description IBC5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 010 2 9 6 4 011 6 9 6 8 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 Table 10-4.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description SDA SCL Hold(stop) SCL Hold(start) SCL START condition STOP condition Figure 10-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 10-5.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-5.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-5.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-5.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-5.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.3.2.3 IIC Control Register (IBCR) Offset Module Base + 0x0002 7 6 5 4 3 IBEN IBIE MS/SL Tx/Rx TXAK R 1 0 0 0 IBSWAI RSTA W Reset 2 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-6. IIC Bus Control Register (IBCR) Read and write anytime Table 10-6. IBCR Field Descriptions Field Description 7 IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-6. IBCR Field Descriptions (continued) Field Description 2 RSTA Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Table 10-7. IBSR Field Descriptions (continued) Field Description 6 IAAS Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.3.2.5 IIC Data I/O Register (IBDR) Offset Module Base + 0x0004 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 R W Reset Figure 10-8. IIC Bus Data I/O Register (IBDR) In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description MSB SCL SDA 1 LSB 2 3 4 5 6 7 Calling Address Read/ Write MSB SDA Start Signal MSB 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal SCL 8 1 XXX 3 4 5 6 7 8 Read/ Write 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 1 XX Ack Bit 9 No Stop Ack Signal Bit MSB 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Calling Address 2 Ack Bit LSB 2 LSB 1 LSB 2 3 5 4 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Repeat
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.4.1.5 Repeated START Signal As shown in Figure 10-9, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 10.4.1.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 10.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine. 10.7 Initialization/Application Information 10.7.1 10.7.1.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description 10.7.1.3 Post-Transfer Software Response Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description MASR DEC BEQ MOVB DEC BNE BSET RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 ENMASR NXMAR BRA BCLR MOVB RTI NXMAR IBCR,#$20 IBDR,RXBUF 10.7.1.
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description Clear IBIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear IBAL Y RXAK=0 ? Last Byte To Be Read ? N N Y N Y Y IAAS=1 ? IAAS=1 ? Y N Address Transfer End Of Addr Cycle (Master Rx) ? N Y Y Y (Read) 2nd Last Byte To Be Read ? SRW=1 ? Write Next Byte To IBDR Generate Stop Signal Set TXAK =1 Generate Stop Signal Read Data From IBDR And Store ACK From Receiver ? N Read Data From
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Chapter 10 Inter-Integrated Circuit (IICV2) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V01.05 19 AUG 2002 Updates after review with verification team. V02.05 15 MAY 2003 Updated version number to match clearcase label V02.06 10 NOV 2010 11.1 11.3.2.24/11-352 11.3.2.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module • • • • • • Edge-aligned or center-aligned PWM signals Half-cycle reload capability Integral reload rates from 1 to 16 Individual software-controlled PWM output Programmable fault protection Polarity control 11.1.2 Modes of Operation Care must be exercised when using this module in the modes listed in Table 11-2. PWM outputs are placed in their inactive states in STOP mode, and optionally under WAIT and FREEZE modes.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module PRSC1 BUS CLOCK LDFQ0 MTG MULTIPLE REGISTERS OR BITS FOR TIMEBASE A, B, OR C LDFQ1 PRSC0 PRESCALER LDFQ2 LDFQ3 PMFMOD REGISTERS PMFVAL0-5 REGISTERS PWMRF PWM GENERATORS A,B,C IPOL EDGE INDEP HALF LDOK PMFCNT REGISTERS PWMEN OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUTCTL0 OUTCTL1 OUTCTL2 OUTCTL3 DT 0—5 OUTCTL4 OUTCTL5 DEADTIME INSERTION MUX, SWAP & CURRENT SENSE PMFDTM REGISTER TOPNEG TOP/BOTTOM GENERATION BOTNEG
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module PWM source selection is based on a number of factors: • State of current sense pins • IPOL bit • OUTCTL bit • Center versus edge aligned SWAPA GENERATE COMPLEMENT AND INSERT DEADTIME IPOLA or ISENS0 or OUTCTL0 PAD0 OUT0 PWM GENERATOR 0 MSK0 OUTCTL0 1 1 INDEPA PWM GENERATOR 1 OUT1 1 FAULT AND POLARITY CONTROL PAD1 1 OUTCTL1 MSK1 Figure 11-2. Detail of Mux, Swap, and Deadtime Functions 11.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3 11.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the PMF module is shown in Figure 11-3. Detailed descriptions of the registers and bits are given in the subsections that follow.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Address Name $000E PMFDTMS $000F PMFCCTL $0010 PMFVAL0 $0011 PMFVAL0 $0012 PMFVAL1 $0013 PMFVAL1 $0014 PMFVAL2 $0015 PMFVAL2 $0016 PMFVAL3 $0017 PMFVAL3 $0018 PMFVAL4 $0019 PMFVAL4 $001A PMFVAL5 $001B PMFVAL5 $001C– $001F Reserved $0020 PMFENCA $0021 PMFFQCA R Bit 7 6 5 4 3 2 1 Bit 0 0 0 DT5 DT4 DT3 DT2 DT1 DT0 0 0 IPOLC IPOLB IPOLA LDOKA PWMRIEA W R 0 ISENS W R PMFVAL0
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Address Name $0022 PMFCNTA $0023 PMFCNTA $0024 PMFMODA $0025 PMFMODA $0026 PMFDTMA $0027 PMFDTMA $0028 PMFENCB $0029 PMFFQCB $002A PMFCNTB $002B PMFCNTB $002C PMFMODB $002D PMFMODB $002E PMFDTMB $002F PMFDTMB $0030 PMFENCC $0031 PMFFQCC Bit 7 R 6 5 4 3 0 2 1 Bit 0 PMFCNTA W R PMFCNTA W R 0 PMFMODA W R PMFMODA W R 0 0 0 0 PMFDTMA W R PMFDTMA W R W PWMENB 0 R 0 0 LDFQB W
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Address Name $0032 PMFCNTC $0033 PMFCNTC $0034 PMFMODC $0035 PMFMODC $0036 PMFDTMC $0037 PMFDTMC $0038– $003F Reserved Bit 7 R 6 5 4 3 0 2 1 Bit 0 PMFCNTC W R PMFCNTC W R 0 PMFMODC W R PMFMODC W R 0 0 0 0 PMFDTMC W R PMFDTMC W R W = Unimplemented or Reserved Figure 11-3. Quick Reference to PMF Registers (Sheet 4 of 4) 11.3.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-3. PMFCFG0 Field Descriptions (continued) Field Description 6 MTG Multiple Timebase Generators — This bit determines the number of timebase counters used. Once set, MTG can be cleared only by reset. If MTG is set, PWM generators B and C and registers $0028 – $0037 are available. The three generators have their own variable frequencies and are not synchronized.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Read anytime. This register cannot be modified after the WP bit is set. A normal PWM output or positive polarity means that the PWM channel outputs high when the counter value is smaller than or equal to the pulse width value and outputs low otherwise. An inverted output or negative polarity means that the PWM channel outputs low when the counter value is smaller than or equal to the pulse width value and outputs high otherwise.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Read and write anytime. Table 11-5. PMFCFG2 Field Descriptions Field 5–0 MSK[5:0] Description Mask PWMx 0 PWMx is unmasked. 1 PWMx is masked and the channel is set to a value of 0 percent duty cycle. where x is 0, 1, 2, 3, 4, and 5 CAUTION When using the TOPNEG/BOTNEG bits and the MSKx bits at the same time, when in complementary mode, it is possible to have both PMF channel outputs of a channel pair set to one. 11.3.2.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-6. PMFCFG3 Field Descriptions (continued) Field Description 2 SWAPC Swap Pair C — This bit can only be written if ENHA is set. 0 No swap. 1 PWM4 and PWM5 are swapped only in complementary mode. 1 SWAPB Swap Pair B — This bit can only be written if ENHA is set. 0 No swap. 1 PWM2 and PWM3 are swapped only in complementary mode. 0 SWAPA Swap Pair A — This bit can only be written if ENHA is set. 0 No swap.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Read anytime. This register cannot be modified after the WP bit is set. Table 11-8. PMFFPIN Field Descriptions Field 6, 4, 2, 0 FPINE[3:0] 11.3.2.7 Description Fault x Pin Enable 0 FAULTx pin is disabled for fault protection. 1 FAULTx pin is enabled for fault protection.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-10. PMFQSMP Field Descriptions Field Description 7–0 QSMP[3:0] Fault x Qualifying Samples — This field indicates the number of consecutive samples taken at the FAULTx pin to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four bus cycles. See Table 11-11. where x is 0, 1, 2 and 3 Table 11-11.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module DMPx3 DMPx2 DMPx1 DMPx0 FAULT0 FAULT1 DISABLE PWM PIN x FAULT2 FAULT3 WHERE x is 0, 1, 2, 3, 4, 5 Figure 11-15. Fault Decoder Table 11-12. Fault Mapping PWM Pin Controlling Register Bits PWM0 DMP03 – DMP00 PWM1 DMP13 – DMP10 PWM2 DMP23 – DMP20 PWM3 DMP33 – DMP30 PWM4 DMP43 – DMP40 PWM5 DMP53 – DMP50 11.3.2.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3.2.11 PMF Output Control Bit Register (PMFOUTB) Address: $000D R 7 6 0 0 W Reset 0 0 5 4 3 2 1 0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-17. PMF Output Control Bit Register (PMFOUTB) Read and write anytime. Table 11-14.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-16. PMFDTMS Field Descriptions Field Description 5–0 DT[5:0} DTx Bits — The DTx bits are grouped in pairs, DT0 and DT1, DT2 and DT3, DT4 and DT5. Each pair reflects the corresponding ISx pin value as sampled at the end of deadtime. 11.3.2.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-18. Correction Method Selection ISENS Correction Method Current status sample on pins IS0, IS1, and IS2(3) At the half cycle in center-aligned operation At the end of the cycle in edge-aligned operation 1. The current status pins can be used as general purpose input/output ports. 2. The polarity of the ISx pin is latched when both the top and bottom PWMs are off.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Read and write anytime. Table 11-20. PMFVAL1 Field Descriptions Field Description 15–0 PMFVAL1 PMF Value 1 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM1 clock period. A value less than or equal to zero deactivates the PWM output for the entire PWM period. A value greater than, or equal to the modulus, activates the PWM output for the entire PWM period. SeeTable 11-37.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-22. PMFVAL3 Field Descriptions Field Description 15–0 PMFVAL3 PMF Value 3 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM3 clock period. A value less than or equal to zero deactivates the PWM output for the entire PWM period. A value greater than, or equal to the modulus, activates the PWM output for the entire PWM period. See Table 11-37.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-24. PMFVAL5 Field Descriptions Field Description 15–0 PMFVAL5 PMF Value 5 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM5 clock period. A value less than or equal to zero deactivates the PWM output for the entire PWM period. A value greater than, or equal to the modulus, activates the PWM output for the entire PWM period. See Table 11-37.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3.2.21 PMF Frequency Control A Register (PMFFQCA) Address: $0021 7 6 R 4 LDFQA W Reset 5 0 0 3 2 HALFA 0 0 1 PRSCA 0 0 0 PWMRFA 0 0 Figure 11-27. PMF Frequency Control A Register (PMFFQCA) Read and write anytime. Table 11-26. PMFFQCA Field Descriptions Field Description 7–4 LDFQA Load Frequency A — This field selects the PWM load frequency according to Table 11-27. See Section 11.4.7.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-28. PWM Prescaler A PRSCA PWM Clock Frequency 00 fbus 01 fbus/2 10 fbus/4 11 fbus/8 11.3.2.22 PMF Counter A Register (PMFCNTA) Address: $0022 15 R 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFCNTA W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-28. PMF Counter A Register (PMFCNTA) Read anytime and writes have no effect.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3.2.24 PMF Deadtime A Register (PMFDTMA) Address: $0026 R 15 14 13 12 0 0 0 0 0 0 0 11 10 9 8 7 6 0 4 3 2 1 0 1 1 1 1 1 PMFDTMA W Reset 5 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 11-30. PMF Deadtime A Register (PMFDTMA) Read anytime. This register cannot be modified after the WP bit is set.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-29. PMFENCB Field Descriptions (continued) Field Description 1 LDOKB Load Okay B — If MTG is clear, this bit reads zero and cannot be written. If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PWMVAL2-3 registers into a set of buffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect at the next PWM reload.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-30. PMFFQCB Field Descriptions (continued) Field Description 0 PWMRFB PWM Reload Flag B — This flag is set at the beginning of every reload cycle regardless of the state of the LDOKB bit. Clear PWMRFB by reading PMFFQCB with PWMRFB set and then writing a logic one to the PWMRFB bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFB has no effect.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3.2.28 PMF Counter Modulo B Register (PMFMODB) Address: $002C 15 R 14 13 12 11 10 9 8 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFMODB W Reset 7 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-34. PMF Counter Modulo B Register (PMFMODB) Read anytime and write only if MTG is set. The 15-bit unsigned value written to this register is the PWM period in PWM clock periods.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3.2.30 PMF Enable Control C Register (PMFENCC) Address: $0030 7 R W PWMENC Reset 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 LDOKC PWMRIEC 0 0 = Unimplemented or Reserved Figure 11-36. PMF Enable Control C Register (PMFENCC) Read anytime and write only if MTG is set. Table 11-33.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-34. PMFFQCC Field Descriptions Field Description 7–4 LDFQC Load Frequency C — This field selects the PWM load frequency according to Table 11-35. See Section 11.4.7.2, “Load Frequency” for more details. Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the load okay bit, LDOKC.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.3.2.32 PMF Counter C Register (PMFCNTC) Address: $0032 15 R 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFCNTC W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-38. PMF Counter C Register (PMFCNTC) Read anytime and writes have no effect. This register displays the state of the 15-bit PWM C counter. 11.3.2.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation. A reset sets the PWM deadtime register to a default value of 0x0FFF, selecting a deadtime of 4096-PWM clock cycles minus one bus clock cycle. NOTE Deadtime is affected by changes to the prescaler value.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module 11.4.3.1 Alignment Each edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs. ALIGNMENT REFERENCE UP/DOWN COUNTER MODULUS = 4 PWM OUTPUT DUTY CYCLE = 50% Figure 11-41. Center-Aligned PWM Output ALIGNMENT REFERENCE UP COUNTER MODULUS = 4 PWM OUTPUT DUTY CYCLE = 50% Figure 11-42.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module COUNT 1 2 3 4 3 2 1 0 UP/DOWN COUNTER MODULUS = 4 PWM CLOCK PERIOD PWM PERIOD = 8 x PWM CLOCK PERIOD Figure 11-43. Center-Aligned PWM Period In an edge-aligned operation, the PWM counter is an up counter. The PWM output resolution is one bus clock cycle. PWM period = PWM modulus × PWM clock period COUNT 1 2 3 4 UP COUNTER MODULUS = 4 PWM CLOCK PERIOD PWM PERIOD = 4 x PWM CLOCK PERIOD Figure 11-44.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module COUNT 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 UP/DOWN COUNTER MODULUS = 4 PWM VALUE = 0 0/4 = 0% PWM VALUE = 1 1/4 = 25% PWM VALUE = 2 2/4 = 50% PWM VALUE = 3 3/4 = 75% PWM VALUE = 4 4/4 = 100% Figure 11-45. Center-Aligned PWM Pulse Width Edge-aligned operation is illustrated in Figure 11-46.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Writing a logic zero to a INDEPx bit configures the PWM output as a pair of complementary channels. The PWM pins are paired as shown in Figure 11-47 in complementary channel operation. PMFVAL0 REGISTER PMFVAL1 REGISTER PAIR A PWM CHANNELS 0 AND 1 TOP BOTTOM PMFVAL2 REGISTER PMFVAL3 REGISTER PAIR B PWM CHANNELS 2 AND 3 TOP BOTTOM PMFVAL4 REGISTER PMFVAL5 REGISTER PAIR C PWM CHANNELS 4 AND 5 TOP BOTTOM Figure 11-47.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module • Swap functionality 11.4.5 Deadtime Generators While in the complementary mode, each PWM pair can be used to drive top/bottom transistors, as shown in Figure 11-49. Ideally, the PWM pairs are an inversion of each other. When the top PWM channel is active, the bottom PWM channel is inactive, and vice versa.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module MODULUS = 4 PWM VALUE = 2 PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 1 PWM1, DEADTIME = 1 Figure 11-50. Deadtime Insertion, Center Alignment MODULUS = 3 PWM VALUE = 1 PWM VALUE = 3 PWM VALUE = 3 PWM VALUE = 3 PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 2 PWM1, DEADTIME = 2 Figure 11-51.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module NOTE The waveform at the pad is delayed by two bus clock cycles for deadtime insertion. 11.4.5.1 Top/Bottom Correction In complementary mode, either the top or the bottom transistor controls the output voltage. However, deadtime has to be inserted to avoid overlap of conducting interval between the top and bottom transistor.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module software is responsible for calculating both compensated PWM values prior to placing them in an oddnumbered/even numbered PWM register pair. Either the odd or the even PMFVAL register controls the pulse width at any given time.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-39. Top/Bottom Manual Correction Bit Logic state Output Control IPOLA 0 PMFVAL0 controls PWM0/PWM1 pair 1 PMFVAL1 controls PWM0/PWM1 pair 0 PMFVAL2 controls PWM2/PWM3 pair 1 PMFVAL3 controls PWM2/PWM3 pair 0 PMFVAL4 controls PWM4/PWM5 pair 1 PMFVAL5 controls PWM4/PWM5 pair IPOLB IPOLC NOTE IPOLx bits are buffered so only one PWM register is used per PWM cycle.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module PWM0 D POSITIVE CURRENT NEGATIVE CURRENT PWM1 PWM0 Q DT0 Q DT1 CLK IS0 PIN D VOLTAGE SENSOR PWM1 CLK Figure 11-55. Current Status Sense Scheme for Deadtime Correction If both D flip-flops latch low, DT0 = 0, DT1 = 0, during deadtime periods if current is large and flowing out of the complementary circuit. See Figure 11-55.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module T B T B V+ DEADTIME PWM TO TOP TRANSISTOR POSITIVE CURRENT NEGATIVE CURRENT PWM TO BOTTOM TRANSISTOR LOAD VOLTAGE WITH HIGH POSITIVE CURRENT LOAD VOLTAGE WITH LOW POSITIVE CURRENT LOAD VOLTAGE WITH HIGH NEGATIVE CURRENT LOAD VOLTAGE WITH NEGATIVE CURRENT T = DEADTIME INTERVAL BEFORE ASSERTION OF TOP PWM B = DEADTIME INTERVAL BEFORE ASSERTION OF BOTTOM PWM Figure 11-56. Output Voltage Waveforms 11.4.5.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module PWM CONTROLLED BY ODD PWMVAL REGISTER A PWM CONTROLLED BY EVEN PWMVAL REGISTER B D Q D CLK IN DEADTIME BOTTOM PWM A/B INITIAL VALUE = 0 ISx PIN TOP PWM DEADTIME GENERATOR Q CLK PWM CYCLE START Figure 11-57.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module DESIRED LOAD VOLTAGE TOP PWM BOTTOM PWM LOAD VOLTAGE Figure 11-60. Correction with Negative Current 11.4.5.4 Output Polarity Output polarity of the PWMs is determined by two options: TOPNEG and BOTNEG. The top polarity option, TOPNEG, controls the polarity of PWM0, PWM2 and PWM4. The bottom polarity option, BOTNEG, controls the polarity of PWM1, PWM3 and PWM5. Positive polarity means when the PWM is active its output is high.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module channel. In a complementary channel operation the even OUTCTL bit is used to enable software output control for the pair. But the OUTCTL bits must be switched in pairs for proper operation. The OUTCTLx and OUTx bits are in the PWM output control register. NOTE During software output control, TOPNEG and BOTNEG still control output polarity. It will take up to 3 clock cycles to see the effect of output control on the PWM output pins.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 11-62. Setting OUT0 with OUTCTL Set in Complementary Mode MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 11-63. Clearing OUT0 with OUTCTL Set In Complementary Mode MC9S12E256 Data Sheet, Rev. 1.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 11-64. Setting OUTCTL with OUT0 Set in Complementary Mode 11.4.7 11.4.7.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module NOTE Loading a new modulus on a half cycle will force the count to the new modulus value minus one on the next clock cycle. Half cycle reloads are possible only in center-aligned mode. Enabling or disabling half-cycle reloads in edge-aligned mode will have no effect on the reload rate. UP/DOWN COUNTER RELOAD CHANGE RELOAD FREQUENCY TO EVERY OPPORTUNITY TO EVERY FOUR OPPORTUNITIES TO EVERY TWO OPPORTUNITIES Figure 11-65.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module HALF = 0, LDFQ[3:0] = 00 = RELOAD EVERY CYCLE UP/DOWN COUNTER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 0 3 2 1 1 3 2 1 0 3 1 1 PWM Figure 11-68. Full-Cycle Center-Aligned PWM Value Loading HALF = 0, LDFQ[3:0] = 00 = RELOAD EVERY CYCLE UP/DOWN COUNTER 1 3 1 1 LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 1 2 1 1 0 2 1 1 1 1 1 1 PWM Figure 11-69.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module HALF = 1, LDFQ[3:0] = 00 = RELOAD EVERY HALF-CYCLE UP/DOWN COUNTER LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 0 3 1 1 0 2 1 1 1 4 1 1 1 1 1 1 0 4 1 1 0 2 1 1 1 4 1 1 PWM Figure 11-71. Half-Cycle Center-Aligned Modulus Loading LDFQ[3:0] = 00 = RELOAD EVERY CYCLE UP ONLY COUNTER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 0 3 2 1 1 3 2 1 0 3 1 1 0 3 1 1 PWM Figure 11-72.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module operation with current-status correction selected, PWM value registers one, three, and five control the outputs for the first PWM cycle. NOTE Even if LDOK is not set, setting PWMEN also sets the PWMRF flag. To prevent a CPU interrupt request, clear the PWMRIE bit before setting PWMEN. Setting PWMEN for the first time after reset without first setting LDOK loads a prescaler divisor of one, a PWM value of $0000, and an unknown modulus.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module When fault protection hardware disables PWM pins, the PWM generator continues to run, only the output pins are deactivated. The fault decoder disables PWM pins selected by the fault logic and the disable mapping register. See Figure 11-15. Each bank of four bits in the disable mapping register control the mapping for a single PWM pin. Refer to Table 11-12.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module • 11, the PWMs are enabled when the next PWM half cycle begins regardless of the state of the logic level detected by the filter at the fault. See Figure 11-77 and Figure 11-78. PWM pins disabled by the FAULT1 pin or the FAULT3 pin are enabled when — Software clears the corresponding FFLAGx flag — The filter detects a logic zero on the fault pin at the start of the next PWM half cycle boundary. See Figure 11-79.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module NOTE Fault protection also applies during software output control when the OUTCTLx bits are set. Fault clearing still occurs at half PWM cycle boundaries while the PWM generator is engaged, PWMEN equals one. But the OUTx bits can control the PWM pins while the PWM generator is off, PWMEN equals zero. Thus, fault clearing occurs at IPbus cycles while the PWM generator is off and at the start of PWM cycles when the generator is engaged.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module Table 11-41. DC Electrical Characteristics (continued) Characteristic Symbol Min Typ Max Unit Output tri-state current high IOZH –10 — 10 µA Output voltage high (at IOHP) VOH VDD – 0.7 — — V Output voltage low (at IOLP) VOL — — 0.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module MC9S12E256 Data Sheet, Rev. 1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.1 Introduction The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B6CV1 module contains the basic features from the HC11 with some of the enhancements incorporated on the HC12, that is center aligned output mode and four available clock sources. The PWM8B6CV1 module has six channels with independent control of left and center aligned outputs on each channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.1.3 Block Diagram PWM8B6C PWM Channels Channel 5 Bus Clock Clock Select PWM Clock Period and Duty PWM5 Counter Channel 4 Period and Duty PWM4 Counter Control Channel 3 Period and Duty PWM3 Counter Channel 2 Enable Period and Duty PWM2 Counter Channel 1 Polarity Period and Duty Alignment PWM1 Counter Channel 0 Period and Duty PWM0 Counter Figure 12-1. PWM8B6CV1 Block Diagram 12.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin This pin serves as waveform output of PWM channel 2. 12.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin This pin serves as waveform output of PWM channel 1. 12.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin This pin serves as waveform output of PWM channel 0. 12.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2 Register Descriptions The following paragraphs describe in detail all the registers and register bits in the PWM8B6CV1 module.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000F PWMCNT3 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x0010 PWMCNT4 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x0011 PWMCNT5 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x0012 PWMPER0 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0013 PWMPER1 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0014 PWMPER2 R W Bit 7 6 5 4 3 2 1 Bit 0 0x0015 PWMPER3 R W Bit 7 6 5 4
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-2. PWME Field Descriptions (continued) Field Description 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-3. PWMPOL Field Descriptions (continued) Field Description 3 PPOL3 Pulse Width Channel 3 Polarity 0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-4. PWMCLK Field Descriptions Field Description 5 PCLK5 Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5. 1 Clock SA is the clock source for PWM channel 5. 4 PCLK4 Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4. 1 Clock SA is the clock source for PWM channel 4. 3 PCLK3 Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-5. PWMPRCLK Field Descriptions Field Description 6:5 PCKB[2:0] Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These three bits determine the rate of clock B, as shown in Table 12-6. 2:0 PCKA[2:0] Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x0004 R 7 6 0 0 5 4 3 2 1 0 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 0 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 12-7. PWM Center Align Enable Register (PWMCAE) Read: anytime Write: anytime NOTE Write these bits only when the corresponding channel is disabled. Table 12-8.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x0005 7 R 6 5 4 3 2 CON45 CON23 CON01 PSWAI PFRZ 0 0 0 0 0 0 1 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 12-8. PWM Control Register (PWMCTL) Read: anytime Write: anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-9. PWMCTL Field Descriptions Field Description 6 CON45 Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high-order byte and channel 5 becomes the low-order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP).
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-9.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.9 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.11 Reserved Registers (PWMSCNTx) The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. Module Base + 0x000A R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-13.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register – 1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x000E 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12-17. PWM Channel Counter Registers (PWMCNT2) Module Base + 0x000F 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12-18.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description • The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x0015 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 12-24. PWM Channel Period Registers (PWMPER3) Module Base + 0x0016 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 12-25.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. Reference Section 12.4.2.3, “PWM Period and Duty,” for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Module Base + 0x001B 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-30. PWM Channel Duty Registers (PWMDTY3) Module Base + 0x001C 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-31.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-10. PWMSDN Field Descriptions Field Description 7 PWMIF PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM5IN input. 1 Change on PWM5IN input 6 PWMIE PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4 Functional Description 12.4.1 PWM Clock Select There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Clock A M U X Clock to PWM Ch 0 Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 PCLK0 8-Bit Down Counter Count = 1 M U X Load PWMSCLA Clock SA DIV 2 PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 8 16 32 64 128 M U X Clock B 4 M U X Clock to PWM Ch 4 Clock B/2, B/4, B/6,....
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.1.2 Clock Scale The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.1.3 Clock Select Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. 12.4.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.2.1 PWM Enable Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.2.4 PWM Timer Counters Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference Figure 12-34 for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 12-35. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description 12.4.2.5 Left Aligned Outputs The PWM timer provides the choice of two types of outputs, left aligned or center aligned outputs. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Shown below is the output waveform generated. E = 100 ns DUTY CYCLE = 75% PERIOD = 400 ns Figure 12-37. PWM Left Aligned Output Example Waveform 12.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 12-40. PWM 16-Bit Mode When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel clock select control bits.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description Table 12-12 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 12-12. 16-bit Concatenation Mode Summary 12.4.2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.1 Introduction The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer contains 4 complete input capture/output compare channels [IOC 7:4] and one pulse accumulator.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.1.3 Block Diagram BUS CLOCK PRESCALER 16-BIT COUNTER TIMER OVERFLOW INTERRUPT REGISTERS CHANNEL 4 INPUT CAPTURE TIMER CHANNEL 4 INTERRUPT OUTPUT COMPARE IOC4 CHANNEL 5 INPUT CAPTURE IOC5 OUTPUT COMPARE TIMER CHANNEL 7 INTERRUPT CHANNEL 6 INPUT CAPTURE OUTPUT COMPARE PA OVERFLOW INTERRUPT PA INPUT INTERRUPT IOC6 CHANNEL 7 16-BIT PULSE ACCUMULATOR INPUT CAPTURE IOC7 OUTPUT COMPARE Figure 13-1.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.2 Signal Description The S12TIM16B4C module has a total four external pins. 13.2.1 Detailed Signal Descriptions 13.2.1.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7.This pin can also be configured as pulse accumulator input. 13.2.1.2 IOC6 — Input Capture and Output Compare Channel 6 This pin serves as input capture or output compare for channel 6. 13.2.1.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description Address Name 0x0000 TIOS 0x0001 CFORC 0x0002 OC7M 0x0003 OC7D 0x0004 TCNT (High) 0x0005 TCNT (Low) 0x0006 TSCR1 0x0007 TTOV 0x0008 TCTL1 0x0009 Reserved 0x000A TCTL3 0x000B Reserved 0x000C TIE 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2 0x0010 ↓ 0x0017 Reserved 0x0018 TC4 (High) 0x0019 TC4 (Low) R W Bit 7 6 5 4 IOS7 IOS6 IOS5 IOS4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 W F
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Chapter 13 Timer (S12TIM16B4CV1) Block Description Address Name 0x001A TC5 (High) 0x001B TC5 (Low) 0x001C TC6 (High) 0x001D TC6(Low) 0x001E TC7 (High) 0x001F TC7 (Low) 0x0020 PACTL 0x0021 PAFLG 0x0022 PACNT (High) 0x0023 PACNT (Low) 0x0024 ↓ 0x002C Reserved 0x002D TIMTST 0x002E ↓ 0x002F Bit 7 6 5 4 3 2 1 Bit 0 tc5 15 tc5 14 tc5 13 tc5 12 tc5 11 tc5 10 tc5 9 tc5 8 tc5 7 tc5 6 tc5 5 tc5 4 tc5 3 tc5 2 tc5 1 tc5 0 tc6 15 tc6 14 tc6 13 tc6 12 tc6 11 tc6 10
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 7 6 5 4 IOS7 IOS6 IOS5 IOS4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 13-3. Timer Input Capture/Output Compare Select (TIOS) Read or write anytime. Table 13-1. TIOS Field Descriptions Field 7–4 IOS[7:4] 13.3.3.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.3 Output Compare 7 Mask Register (OC7M) Module Base + 0x0002 7 6 5 4 OC7M7 OC7M6 OC7M5 OC7M4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 13-5. Output Compare 7 Mask Register (OC7M) Read or write anytime. Table 13-3.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.5 Timer Count Register (TCNT) Module Base + 0x0004–0x0005 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tcnt 15 tcnt 14 tcnt 13 tcnt 12 tcnt 11 tcnt 10 tcnt 9 tcnt 8 tcnt 7 tcnt 6 tcnt 5 tcnt 4 tcnt 3 tcnt 2 tcnt 1 tcnt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Figure 13-7. Timer Count Register (TCNT) Read anytime. Writable only in special mode (refer for SOC guide for special modes).
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Chapter 13 Timer (S12TIM16B4CV1) Block Description Table 13-5. TSCR1 Field Descriptions (continued) Field Description 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing. 1 For TFLG1 register, a read from an input capture or a write to the output compare channel [TC 7:4] causes the corresponding channel flag, CnF, to be cleared.For TFLG2 register, any access to the TCNT register clears the TOF flag. Any access to the PACNT registers clears the PAOVF and PAIF bits in the PAFLG register.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.8 Timer Control Register 1 (TCTL1) Module Base + 0x0008 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 R W Reset Figure 13-10. Timer Control Register 1 (TCTL1) Read or write anytime. Table 13-7.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description IOSx is the register TIOS bit x, OC7Mx is the register OC7M bit x, TCx is timer Input Capture/Output Compare register, IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. MC9S12E256 Data Sheet, Rev. 1.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.9 Timer Control Register 3 (TCTL3) Module Base + 0x000A 7 6 5 4 3 2 1 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 R W Reset Figure 13-11. Timer Control Register 3 (TCTL3) Read or write anytime. Table 13-10.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R 6 5 4 0 0 0 TOI 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 13-13. Timer System Control Register 2 (TSCR2) Read or write anytime. Table 13-13. TSCR2 Field Descriptions Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Hardware Interrupt request inhibited.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E 7 6 5 4 C7F C6F C5F C4F 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 13-14. Main Timer Interrupt Flag 1 (TFLG1) Read anytime. Table 13-15. TFLG1 Field Descriptions Field Description 7–4 C[7:4]F Input Capture/Output Compare Channel Flag — These flags are set when an input capture or output compare event occurs.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 R 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 13-17. 16-Bit Pulse Accumulator Control Register (PACTL) Read: any time Write: any time Table 13-17. PACTL Field Descriptions Field Description 6 PAEN Pulse Accumulator System Enable — PAEN is independent from TEN.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description Table 13-18. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Divide by 64 clock enabled with pin high level 1 1 Divide by 64 clock enabled with pin low level Table 13-19.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.3.3.17 Pulse Accumulators Count Registers (PACNT) Module Base + 0x0022–0x0023 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-19. Pulse Accumulators Count Registers (PACNT) Read or write any time.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description BUS CLOCK CLK[1:0] PR[2:1:0] CHANNEL 7 OUTPUT COMPARE PACLK PACLK/256 PACLK/65536 MUX TCRE PRESCALER CXI TCNT(HI):TCNT(LO) CXF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 4 16-BIT COMPARATOR C4F TC4 EDG4A EDGE DETECT EDG4B C4F OM:OL4 CH. 4 CAPTURE IOC4 PIN LOGIC TOV4 CH.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.4.3 Input Capture Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCn. The minimum pulse width for the input capture input is greater than two bus clocks.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.4.5 Pulse Accumulator The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes: • Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, IOC7. • Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two bus clocks.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description NOTE The PACNT input and timer channel 7 use the same pin IOC7. To use the IOC7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare 7 mask bit, OC7M7. The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin, IOC7 since the last reset. The PAOVF bit is set when the accumulator rolls over from $FFFF to $0000.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description Table 13-21.
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Chapter 13 Timer (S12TIM16B4CV1) Block Description 13.6.2 Description of Interrupt Operation The S12TIM16B4C uses a total of 7 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. More information on interrupt vector offsets and interrupt numbers can be found in the System on Chip Guide. 13.6.2.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.1 Introduction The VREG3V3V2 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical). 14.1.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.1.3 Block Diagram Figure 14-1 shows the function principle of VREG3V3V2 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.2 External Signal Description Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 14-1 shows all signals of VREG3V3V2 associated with pins. Table 14-1.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.2.3 VDD, VSS — Regulator Output1 (Core Logic) Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In shutdown mode an external supply at VDD/VSS can replace the voltage regulator. 14.2.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.3.2 Register Descriptions The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual bits. 14.3.2.1 VREG3V3V2 — Control Register (VREGCTRL) The VREGCTRL register allows to separately enable features of VREG3V3V2. Module Base + 0x0000 R 7 6 5 4 3 2 0 0 0 0 0 LVDS 1 0 LVIE LVIF 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-2.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.4.1 REG — Regulator Core VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1 providing the supply at VDD/VSS is explained. The principle is also valid for REG2.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description 14.5 Resets This subsection describes how VREG3V3V2 controls the reset of the MCU.The reset values of registers and signals are provided in Section 14.3, “Memory Map and Register Definition”. Possible reset sources are listed in Table 14-4. Table 14-4. VREG3V3V2 — Reset Sources Reset Source 14.5.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in Figure 15-1. HOST SYSTEM BKGD 16-BIT SHIFT REGISTER ADDRESS ENTAG BDMACT INSTRUCTION DECODE AND EXECUTION TRACE SDV ENBDM BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS STANDARD BDM FIRMWARE LOOKUP TABLE CLKSW Figure 15-1.
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Chapter 15 Background Debug Module (BDMV4) Block Description • • • • • • • Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from the standard BDM firmware lookup table Instruction tagging capability Software control of BDM operation during wait mode Software selectable clocks When secured, hardware commands are allowed to access the register space in special single-chip mode, if the FLASH and EEPROM
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Chapter 15 Background Debug Module (BDMV4) Block Description • • • • • BKGD — Background interface pin TAGHI — High byte instruction tagging pin TAGLO — Low byte instruction tagging pin BKGD and TAGHI share the same pin. TAGLO and LSTRB share the same pin. NOTE Generally these pins are shared as described, but it is best to check the device overview chapter to make certain. All MCUs at the time of this writing have followed this pin sharing scheme. 15.2.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.3 Memory Map and Register Definition A summary of the registers associated with the BDM is shown in Figure 15-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow. 15.3.1 Module Memory Map Table 15-1.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.3.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.3.2.1 BDM Status Register (BDMSTS) 0xFF01 7 6 R 5 BDMACT ENBDM 4 3 SDV TRACE ENTAG 2 1 0 UNSEC 0 02 0 0 0 0 0 0 0 CLKSW W Reset: Special single-chip mode: Special peripheral mode: All other modes: 11 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 0 0 0 0 = Implemented (do not alter) Figure 15-3.
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Chapter 15 Background Debug Module (BDMV4) Block Description Table 15-2. BDMSTS Field Descriptions Field Description 7 ENBDM Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode.
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Chapter 15 Background Debug Module (BDMV4) Block Description Table 15-2. BDMSTS Field Descriptions (continued) Field Description 2 CLKSW Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.3.2.2 BDM CCR Holding Register (BDMCCR) 0xFF06 7 6 5 4 3 2 1 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 0 R W Reset Figure 15-4. BDM CCR Holding Register (BDMCCR) Read: All modes Write: All modes NOTE When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 15.4.3, “BDM Hardware Commands.” Target system memory includes all memory that is accessible by the CPU.
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Chapter 15 Background Debug Module (BDMV4) Block Description sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed.
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Chapter 15 Background Debug Module (BDMV4) Block Description The BDM hardware commands are listed in Table 15-5. Table 15-5. Hardware Commands Opcode (hex) Data Description BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable handshake. This command does not issue an ACK pulse.
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Chapter 15 Background Debug Module (BDMV4) Block Description firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 15-6. Table 15-6. Firmware Commands Command1 Opcode (hex) Data Description READ_NEXT 62 16-bit data out Increment X by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator.
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Chapter 15 Background Debug Module (BDMV4) Block Description NOTE 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out.
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Chapter 15 Background Debug Module (BDMV4) Block Description HARDWARE READ 8 BITS AT ∼16 TC/BIT 16 BITS AT ∼16 TC/BIT COMMAND ADDRESS 150-BC DELAY 16 BITS AT ∼16 TC/BIT DATA NEXT COMMAND 150-BC DELAY HARDWARE WRITE COMMAND ADDRESS DATA NEXT COMMAND 44-BC DELAY FIRMWARE READ COMMAND NEXT COMMAND DATA 32-BC DELAY FIRMWARE WRITE COMMAND DATA NEXT COMMAND 64-BC DELAY GO, TRACE COMMAND NEXT COMMAND BC = BUS CLOCK CYCLES TC = TARGET CLOCK CYCLES Figure 15-6. BDM Command Structure 15.4.
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Chapter 15 Background Debug Module (BDMV4) Block Description clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 15-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time.
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Chapter 15 Background Debug Module (BDMV4) Block Description CLOCK TARGET SYSTEM HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 15-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 15-9 shows the host receiving a logic 0 from the target.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU.
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Chapter 15 Background Debug Module (BDMV4) Block Description Figure 15-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse.
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Chapter 15 Background Debug Module (BDMV4) Block Description READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST (OUT OF SCALE) BKGD PIN READ_BYTE SYNC RESPONSE FROM THE TARGET (OUT OF SCALE) MEMORY ADDRESS HOST READ_STATUS TARGET HOST TARGET BDM DECODE AND STARTS TO EXECUTES THE READ_BYTE CMD NEW BDM COMMAND HOST TARGET NEW BDM COMMAND Figure 15-12. ACK Abort Procedure at the Command Level Figure 15-13 shows a conflict between the ACK pulse and the SYNC request pulse.
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Chapter 15 Background Debug Module (BDMV4) Block Description The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. • ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol.
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Chapter 15 Background Debug Module (BDMV4) Block Description 15.4.9 SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1.
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Chapter 15 Background Debug Module (BDMV4) Block Description If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. 15.4.11 Instruction Tagging The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer.
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Chapter 15 Background Debug Module (BDMV4) Block Description If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDC is running in a frequency much greater than the CPU frequency.
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Chapter 15 Background Debug Module (BDMV4) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 16 Debug Module (DBGV1) Block Description 16.1 Introduction This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform. The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP mode) and furthermore provides an on-chip trace buffer with flexible triggering capability (DBG mode). The DBG module provides for non-intrusive debug of application software. The DBG module is optimized for the HCS12 16-bit architecture. 16.1.
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Chapter 16 Debug Module (DBGV1) Block Description The DBG in DBG mode includes these distinctive features: • Three comparators (A, B, and C) — Dual mode, comparators A and B used to compare addresses — Full mode, comparator A compares address and comparator B compares data — Can be used as trigger and/or breakpoint — Comparator C used in LOOP1 capture mode or as additional breakpoint • Four capture modes — Normal mode, change-of-flow information is captured based on trigger specification — Loop1 mode, comp
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Chapter 16 Debug Module (DBGV1) Block Description — — — — 16.1.2 Data associated with event B trigger modes Detail report mode stores address and data for all cycles except program (P) and free (f) cycles Current instruction address when in profiling mode BGND is not considered a change-of-flow (cof) by the debugger Modes of Operation There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive of the other and selected via a software programmable control bit.
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Chapter 16 Debug Module (DBGV1) Block Description CLOCKS AND CONTROL SIGNALS BKP CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS ...... RESULTS SIGNALS CONTROL SIGNALS READ/WRITE CONTROL CONTROL BITS ......
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Chapter 16 Debug Module (DBGV1) Block Description DBG READ DATA BUS ADDRESS BUS ADDRESS/DATA/CONTROL REGISTERS CONTROL WRITE DATA BUS READ DATA BUS READ/WRITE TRACER BUFFER CONTROL LOGIC MATCH_A COMPARATOR A MATCH_B COMPARATOR B DBG MODE ENABLE CONTROL MATCH_C LOOP1 COMPARATOR C TAG FORCE CHANGE-OF-FLOW INDICATORS MCU IN BDM DETAIL EVENT ONLY STORE CPU PROGRAM COUNTER POINTER INSTRUCTION LAST CYCLE M U X REGISTER BUS CLOCK WRITE DATA BUS M U X READ DATA BUS M U X LAST INSTRUCTION ADDRE
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Chapter 16 Debug Module (DBGV1) Block Description 16.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in Figure 16-3. Detailed descriptions of the registers and bits are given in the subsections that follow. 16.3.1 Module Memory Map Table 16-2.
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Chapter 16 Debug Module (DBGV1) Block Description Name1 R 0x0022 DBGTBH W 0x0023 DBGTBL W 0x0024 DBGCNT R R R W 0x0026 DBGCCH(2) W 0x0028 DBGC2 BKPCT0 0x0029 DBGC3 BKPCT1 0x002A DBGCAX BKP0X 0x002B DBGCAH BKP0H 0x002C DBGCAL BKP0L 0x002D DBGCBX BKP1X 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBF 0 CNT W 0x0025 DBGCCX(2) 0x0027 DBGCCL(2) Bit 7 R R W PAGSEL EXTCMP Bit 15 14 13 12 11
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Chapter 16 Debug Module (DBGV1) Block Description 1 The DBG module is designed for backwards compatibility to existing BKP modules. Register and bit names have changed from the BKP module. This column shows the DBG register name, as well as the BKP register name for reference. 2 Comparator C can be used to enhance the BKP mode by providing a third breakpoint. 16.3.2.1 Debug Control Register 1 (DBGC1) NOTE All bits are used in DBG mode only.
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Chapter 16 Debug Module (DBGV1) Block Description Table 16-3. DBGC1 Field Descriptions (continued) Field Description 4 BEGIN Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace buffer. See Section 16.4.2.8.1, “Storing with Begin-Trigger,” and Section 16.4.2.8.2, “Storing with End-Trigger,” for more details.
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Chapter 16 Debug Module (DBGV1) Block Description 16.3.2.2 Debug Status and Control Register (DBGSC) Module Base + 0x0021 Starting address location affected by INITRG register setting. R 7 6 5 4 AF BF CF 0 3 2 1 0 0 0 TRG W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-5. Debug Status and Control Register (DBGSC) Table 16-5. DBGSC Field Descriptions Field Description 7 AF Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming.
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Chapter 16 Debug Module (DBGV1) Block Description 16.3.2.3 Debug Trace Buffer Register (DBGTB) Module Base + 0x0022 Starting address location affected by INITRG register setting. R 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 u u u u u u u u W Reset = Unimplemented or Reserved Figure 16-6. Debug Trace Buffer Register High (DBGTBH) Module Base + 0x0023 Starting address location affected by INITRG register setting.
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Chapter 16 Debug Module (DBGV1) Block Description 16.3.2.4 Debug Count Register (DBGCNT) Module Base + 0x0024 Starting address location affected by INITRG register setting. R 7 6 TBF 0 0 0 5 4 3 2 1 0 0 0 0 CNT W Reset 0 0 0 = Unimplemented or Reserved Figure 16-8. Debug Count Register (DBGCNT) Table 16-8. DBGCNT Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was last armed.
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Chapter 16 Debug Module (DBGV1) Block Description 16.3.2.5 Debug Comparator C Extended Register (DBGCCX) Module Base + 0x0025 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 16-9. Debug Comparator C Extended Register (DBGCCX) Table 16-10. DBGCCX Field Descriptions Field Description 7:6 PAGSEL Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 16-11.
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Chapter 16 Debug Module (DBGV1) Block Description DBGCXX 7 DBGCXH[15:12] EXTCMP 6 BIT 15 BIT 14 XAB16 XAB15 XAB14 PIX2 PIX1 PIX0 0 5 0 4 3 2 1 BIT 0 XAB21 XAB20 XAB19 XAB18 XAB17 PIX7 PIX6 PIX5 PIX4 PIX3 BIT 13 BIT 12 BKP/DBG MODE PAGSEL SEE NOTE 1 PORTK/XAB PPAGE SEE NOTE 2 NOTES: 1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 16-11. 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
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Chapter 16 Debug Module (DBGV1) Block Description Table 16-12. DBGCC Field Descriptions Field Description 15:0 Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare the address bus bits [15:0] to a logic 1 or logic 0. See Table 16-13. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode. Table 16-13.
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Chapter 16 Debug Module (DBGV1) Block Description Table 16-14. DBGC2 Field Descriptions (continued) Field Description 4 TAGAB Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint.
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Chapter 16 Debug Module (DBGV1) Block Description Table 16-15. DBGC3 Field Descriptions Field Description 7:6 Breakpoint Mask High Byte for First Address — In dual or full mode, these bits may be used to mask (disable) BKAMB[H:L] the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in Table 16-16. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare.
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Chapter 16 Debug Module (DBGV1) Block Description Table 16-15. DBGC3 Field Descriptions (continued) Field Description 1 RWBEN Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled for comparator B. See Section 16.4.2.1.1, “Read or Write Comparison,” for more information. This bit is not useful for tagged operations.
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Chapter 16 Debug Module (DBGV1) Block Description 16.3.2.9 Debug Comparator A Extended Register (DBGCAX) Module Base + 0x002A Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 16-15. Debug Comparator A Extended Register (DBGCAX) Table 16-19. DBGCAX Field Descriptions Field 7:6 PAGSEL Description Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 16-20.
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Chapter 16 Debug Module (DBGV1) Block Description 0 EXTCMP 0 5 4 3 2 1 BIT 0 SEE NOTE 1 PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 PPAGE BKP MODE PAGSEL DBGCXX SEE NOTE 2 NOTES: 1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state). 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Figure 16-16. Comparators A and B Extended Comparison in BKP Mode 16.3.2.
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Chapter 16 Debug Module (DBGV1) Block Description 16.3.2.11 Debug Comparator B Extended Register (DBGCBX) Module Base + 0x002D 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 16-19. Debug Comparator B Extended Register (DBGCBX) Table 16-22. DBGCBX Field Descriptions Field 7:6 PAGSEL Description Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 16-11.
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Chapter 16 Debug Module (DBGV1) Block Description Module Base + 0x002F Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 16-21. Debug Comparator B Register Low (DBGCBL) Table 16-23.
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Chapter 16 Debug Module (DBGV1) Block Description DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. The BKxMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion.
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Chapter 16 Debug Module (DBGV1) Block Description NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
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Chapter 16 Debug Module (DBGV1) Block Description control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to match the upper addresses as shown in Table 16-11. NOTE If a tagged-type C breakpoint is set at the same address as an A/B tagged-type trigger (including the initial entry in an inside or outside range trigger), the C breakpoint will have priority and the trigger will not be recognized. 16.4.2.1.
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Chapter 16 Debug Module (DBGV1) Block Description 16.4.2.3 Begin- and End-Trigger The definitions of begin- and end-trigger as used in the DBG module are as follows: • Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are filled. • End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected. 16.4.2.
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Chapter 16 Debug Module (DBGV1) Block Description least six addresses higher than address A (or B is lower than A) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 16.4.2.5.4 Event-Only B (Store Data) In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in DBGC1 is ignored.
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Chapter 16 Debug Module (DBGV1) Block Description 16.4.2.5.8 Inside Range (A ≤ address ≤ B) In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries.
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Chapter 16 Debug Module (DBGV1) Block Description 16.4.2.6 Capture Modes The DBG in DBG mode can operate in four capture modes. These modes are described in the following subsections. 16.4.2.6.1 Normal Mode In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow information or data will be stored depending on TRG in DBGSC. 16.4.2.6.
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Chapter 16 Debug Module (DBGV1) Block Description 16.4.2.6.3 Detail Mode In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where his code was in error. 16.4.2.6.
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Chapter 16 Debug Module (DBGV1) Block Description the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace buffer. 16.4.2.9 Reading Data from Trace Buffer The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid words can be determined.
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Chapter 16 Debug Module (DBGV1) Block Description Table 16-26.
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Chapter 16 Debug Module (DBGV1) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 16 Debug Module (DBGV1) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 17 Interrupt (INTV1) Block Description 17.1 Introduction This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in Figure 17-1.
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Chapter 17 Interrupt (INTV1) Block Description The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug mode request, and three system reset vector requests. All interrupt related exception requests are managed by the interrupt sub-block (INT). 17.1.
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Chapter 17 Interrupt (INTV1) Block Description 17.2 External Signal Description Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data. 17.3 Memory Map and Register Definition Detailed descriptions of the registers and associated bits are given in the subsections that follow. 17.3.1 Module Memory Map Table 17-1.
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Chapter 17 Interrupt (INTV1) Block Description Table 17-2. ITCR Field Descriptions Field Description 4 WRTINT Write to the Interrupt Test Registers Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs. 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead.
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Chapter 17 Interrupt (INTV1) Block Description Table 17-3. ITEST Field Descriptions Field Description 7:0 INT[E:0] Interrupt TEST Bits — These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0.
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Chapter 17 Interrupt (INTV1) Block Description 17.4.1 Low-Power Modes The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections. 17.4.1.1 Operation in Run Mode The INT does not contain any options for reducing power in run mode. 17.4.1.
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Chapter 17 Interrupt (INTV1) Block Description 17.6.3 Interrupt Priority Decoder The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector.
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Chapter 17 Interrupt (INTV1) Block Description MC9S12E256 Data Sheet, Rev. 1.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.1 Introduction This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory map controller (MMC) sub-blocks. Figure 18-1 is a block diagram of the MEBI. In Figure 18-1, the signals on the right hand side represent pins that are accessible externally. On some chips, these may not all be bonded out.
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Internal Bus Addr[19:0] EXT BUS I/F CTL Data[15:0] ADDR DATA Port K ADDR PK[7:0]/ECS/XCS/X[19:14] Port A REGS PA[7:0]/A[15:8]/ D[15:8]/D[7:0] Port B Chapter 18 Multiplexed External Bus Interface (MEBIV3) PB[7:0]/A[7:0]/ D[7:0] (Control) ADDR DATA CPU pipe info PIPE CTL IRQ interrupt XIRQ interrupt IRQ CTL TAG CTL BDM tag info mode Port E ECLK CTL PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ BKGD BKGD/MODC/TAGHI Control signal(s) Data signal (
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.1.2 • • • • • • • • 18.2 Modes of Operation Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) . Table 18-1. External System Pins Associated With MEBI Pin Name BKGD/MODC/ TAGHI PA7/A15/D15/D7 thru PA0/A8/D8/D0 PB7/A7/D7 thru PB0/A0/D0 PE7/NOACC PE6/IPIPE1/ MODB/CLKTO PE5/IPIPE0/MODA Pin Functions Description MODC At the rising edge on RESET, the state of this pin is registered into the MODC bit to set the mode. (This pin always has an internal pullup.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-1. External System Pins Associated With MEBI (continued) Pin Name PE4/ECLK PE3/LSTRB/ TAGLO PE2/R/W PE1/IRQ PE0/XIRQ PK7/ECS PK6/XCS PK5/X19 thru PK0/X14 Pin Functions Description PE4 General-purpose I/O pin, see PORTE and DDRE registers.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.1 Module Memory Map Table 18-2. MEBI Memory Map Address Offset 18.3.2 18.3.2.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Read: Anytime when register is in the map Write: Anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines the primary direction of each pin.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) NOTE To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register. MC9S12E256 Data Sheet, Rev. 1.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.3 Data Direction Register A (DDRA) Module Base + 0x0002 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 18-4. Data Direction Register A (DDRA) Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port A.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.4 Data Direction Register B (DDRB) Module Base + 0x0003 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 18-5. Data Direction Register B (DDRB) Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port B.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.5 Reserved Registers Module Base + 0x0004 Starting address location affected by INITRG register setting. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-6. Reserved Register Module Base + 0x0005 Starting address location affected by INITRG register setting.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) These register locations are not used (reserved). All unused registers and bits in this block return logic 0s when read. Writes to these registers have no effect. These registers are not in the on-chip map in special peripheral mode. 18.3.2.6 Port E Data Register (PORTE) Module Base + 0x0008 Starting address location affected by INITRG register setting.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) NOTE To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register. 18.3.2.7 Data Direction Register E (DDRE) Module Base + 0x0009 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 Bit 7 6 5 4 3 Bit 2 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-11.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.8 Port E Assignment Register (PEAR) Module Base + 0x000A Starting address location affected by INITRG register setting.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-6. PEAR Field Descriptions Field Description 7 NOACCE CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle. This bit has no effect in single-chip or special peripheral modes.
PAGE 536
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.9 Mode Register (MODE) Module Base + 0x000B Starting address location affected by INITRG register setting.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-7. MODE Field Descriptions Field Description 7:5 MOD[C:A] Mode Select Bits — These bits indicate the current operating mode. If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then MODC, MODB, and MODA are writable with the exception that you cannot change to or from special peripheral mode If MODC = 1, MODB = 0, and MODA = 0, then MODC is write never.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-8.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE These bits have no effect when the associated pin(s) are outputs. (The pull resistors are inactive.) Table 18-9. PUCR Field Descriptions Field Description 7 PUPKE Pull resistors Port K Enable 0 Port K pull resistors are disabled. 1 Enable pull resistors for port K input pins.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-10. RDRIV Field Descriptions Field Description 7 RDRK Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. 4 RDPE Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. 1 RDPB Reduced Drive of Port B 0 All port B output pins have full drive enabled.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.13 Reserved Register Module Base + 0x000F Starting address location affected by INITRG register setting. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-17. Reserved Register This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to this register have no effect.
PAGE 542
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.15 Port K Data Register (PORTK) Module Base + 0x0032 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 ECS XCS XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 R W Reset Alternate Pin Function Figure 18-19. Port K Data Register (PORTK) Read: Anytime Write: Anytime This port is associated with the internal memory expansion emulation pins.
PAGE 543
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.16 Port K Data Direction Register (DDRK) Module Base + 0x0033 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 18-20. Port K Data Direction Register (DDRK) Read: Anytime Write: Anytime This register determines the primary direction for each port K pin configured as general-purpose I/O.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-15. Access Type vs. Bus Control Pins 18.4.
PAGE 545
Chapter 18 Multiplexed External Bus Interface (MEBIV3) There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent.
PAGE 546
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.4.3.1.2 Normal Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull resistors enabled).
PAGE 547
Chapter 18 Multiplexed External Bus Interface (MEBIV3) The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system.
PAGE 548
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.4.3.2 Special Operating Modes There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 18.4.3.2.1 Special Single-Chip Mode When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions. 18.4.4 Internal Visibility Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) MC9S12E256 Data Sheet, Rev. 1.
PAGE 551
Chapter 19 Module Mapping Control (MMCV4) Block Description 19.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in Figure 19-1.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.1.
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Chapter 19 Module Mapping Control (MMCV4) Block Description Table 19-1. MMC Memory Map (continued) Address Offset 0x0017 Register Reserved Access — . . . . — 0x001C Memory Size Register 0 (MEMSIZ0) R 0x001D Memory Size Register 1 (MEMSIZ1) R . . . . 0x0030 Program Page Index Register (PPAGE) 0x0031 Reserved R/W — MC9S12E256 Data Sheet, Rev. 1.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.2.1 Initialization of Internal RAM Position Register (INITRM) Module Base + 0x0010 Starting address location affected by INITRG register setting. 7 6 5 4 3 RAM15 RAM14 RAM13 RAM12 RAM11 0 0 0 0 1 R 2 1 0 0 0 RAMHAL W Reset 0 0 1 = Unimplemented or Reserved Figure 19-3.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.2.2 Initialization of Internal Registers Position Register (INITRG) Module Base + 0x0011 Starting address location affected by INITRG register setting. 7 R 6 5 4 3 REG14 REG13 REG12 REG11 0 0 0 0 0 2 1 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 19-4.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.2.3 Initialization of Internal EEPROM Position Register (INITEE) Module Base + 0x0012 Starting address location affected by INITRG register setting. 7 6 5 4 3 EE15 EE14 EE13 EE12 EE11 — — — — — R 2 1 0 0 0 EEON W Reset1 — — — 1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.2.4 Miscellaneous System Control Register (MISC) Module Base + 0x0013 Starting address location affected by INITRG register setting. R 7 6 5 4 0 0 0 0 3 2 1 0 EXSTR1 EXSTR0 ROMHM ROMON W Reset: Expanded or Emulation 0 0 0 0 1 1 0 —1 Reset: Peripheral or Single Chip 0 0 0 0 1 1 0 1 Reset: Special Test 0 0 0 0 1 1 0 0 1. The reset state of this bit is determined at the chip integration level.
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Chapter 19 Module Mapping Control (MMCV4) Block Description Table 19-6. External Stretch Bit Definition 19.3.2.5 Stretch Bit EXSTR1 Stretch Bit EXSTR0 Number of E Clocks Stretched 0 0 0 0 1 1 1 0 2 1 1 3 Reserved Test Register 0 (MTST0) Module Base + 0x0014 Starting address location affected by INITRG register setting. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-7.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.2.7 Memory Size Register 0 (MEMSIZ0) Module Base + 0x001C Starting address location affected by INITRG register setting. 7 R REG_SW0 6 5 4 3 2 1 0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0 — — — — — — — W Reset — = Unimplemented or Reserved Figure 19-9. Memory Size Register 0 (MEMSIZ0) Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section.
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Chapter 19 Module Mapping Control (MMCV4) Block Description Table 19-9.
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Chapter 19 Module Mapping Control (MMCV4) Block Description Table 19-10. MEMSIZ0 Field Descriptions Field Description 7:6 Allocated System FLASH or ROM Physical Memory Space — The allocated system FLASH or ROM ROM_SW[1:0] physical memory space is as given in Table 19-11. 1:0 Allocated Off-Chip FLASH or ROM Memory Space — The allocated off-chip FLASH or ROM memory space PAG_SW[1:0] size is as given in Table 19-12. Table 19-11.
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Chapter 19 Module Mapping Control (MMCV4) Block Description 19.3.2.9 Program Page Index Register (PPAGE) Module Base + 0x0030 Starting address location affected by INITRG register setting. R 7 6 0 0 5 4 3 2 1 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 — — — — — — W Reset1 — — 1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved Figure 19-11.
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Chapter 19 Module Mapping Control (MMCV4) Block Description Table 19-14. Program Page Index Register Bits 19.4 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Program Space Selected 0 0 0 0 0 0 16K page 0 0 0 0 0 0 1 16K page 1 0 0 0 0 1 0 16K page 2 0 0 0 0 1 1 16K page 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 19 Module Mapping Control (MMCV4) Block Description vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table 19-15. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active.
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Chapter 19 Module Mapping Control (MMCV4) Block Description unimplemented locations within the register space or to locations that are removed from the map (i.e., ports A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this pin is used for general purpose I/O. 19.4.3 Memory Expansion The HCS12 core architecture limits the physical address space available to 64K bytes.
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Chapter 19 Module Mapping Control (MMCV4) Block Description The PPAGE register holds the page select value for the program page window. The value of the PPAGE register can be manipulated by normal read and write (some devices don’t allow writes in some modes) instructions as well as the CALL and RTC instructions. Control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the 64K byte physical address space.
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Chapter 19 Module Mapping Control (MMCV4) Block Description During the execution of an RTC instruction, the CPU: • Pulls the old PPAGE value from the stack • Pulls the 16-bit return address from the stack and loads it into the PC • Writes the old PPAGE value into the PPAGE register • Refills the queue and resumes execution at the return address This sequence is uninterruptable; an RTC can be executed from anywhere in memory, even from a different page of extended memory in the expansion window.
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Chapter 19 Module Mapping Control (MMCV4) Block Description Table 19-20. 48K Byte Physical FLASH/ROM Allocated Address Space Page Window Access ROMHM ECS XAB19:14 0x0000–0x3FFF N/A N/A 1 0x3D 0x4000–0x7FFF N/A 0 0 0x3E N/A 1 1 0x8000–0xBFFF 0xC000–0xFFFF External N/A 1 Internal N/A 0 N/A N/A 0 PIX[5:0] 0x3F Table 19-21.
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Chapter 19 Module Mapping Control (MMCV4) Block Description A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in Figure 19-12.
PAGE 571
Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. The part is specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the part is not tested in production test in the intermediate range.
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Appendix A Electrical Characteristics A.1.2 Power Supply The MC9S12E-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and D/A converter. The VDDX, VSSX pair supplies the I/O pins The VDDR, VSSR pair supplies the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the internal logic. VDDPLL, VSSPLL supply the oscillator and the PLL.
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Appendix A Electrical Characteristics A.1.3 Pins There are four groups of functional pins. A.1.3.1 3.3V/5V I/O Pins Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some of the functionality may be disabled. A.1.3.2 Analog Reference This group of pins is comprised of the VRH and VRL pins.
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Appendix A Electrical Characteristics A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.
PAGE 575
Appendix A Electrical Characteristics A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification.
PAGE 576
Appendix A Electrical Characteristics A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4.
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Appendix A Electrical Characteristics Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P P = I INT IO = DD ⋅V DD +I DDPLL ⋅V DDPLL +I DDA ⋅V DDA ∑i RDSON ⋅ IIOi2 Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.
PAGE 578
Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable, e.g., not all pins feature pull up/down resistances. Table A-6. 5V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Symbol Min Typ Max Unit Input High Voltage VIH 0.65*VDD5 — — V T Input High Voltage VIH — — VDD5 + 0.3 V P Input Low Voltage VIL — — 0.
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Appendix A Electrical Characteristics Table A-7. Preliminary 3.3V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Symbol Min Typ Max Unit Input High Voltage VIH 0.65*VDD5 — — V T Input High Voltage VIH — — VDD5 + 0.3 V P Input Low Voltage VIL — — 0.35*VDD5 V T Input Low Voltage VIL VSS5 – 0.
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Appendix A Electrical Characteristics A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals.
PAGE 581
Appendix A Electrical Characteristics A.2 Voltage Regulator This section describes the characteristics of the on chip voltage regulator. Table A-9. Voltage Regulator Electrical Parameters Num C 1 P Input Voltages 3 P 4 5 6 7 P P P C Characteristic Symbol Min Typ Max Unit VVDDR,A 2.97 — 5.5 V Output Voltage Core Full Performance Mode VDD 2.35 2.5 2.75 V Output Voltage PLL Full Performance Mode VDDPLL 2.35 2.5 2.
PAGE 582
Appendix A Electrical Characteristics A.2.1 Chip Power-up and LVI/LVR Graphical Explanation Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1. V VDDA VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR Figure A-1. Voltage Regulator — Chip Power-up and Voltage Drops (not scaled) MC9S12E256 Data Sheet, Rev. 1.
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Appendix A Electrical Characteristics A.2.2 Output Loads A.2.2.1 Resistive Loads The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads. A.2.2.2 Capacitive Loads The capacitive loads are specified in Table A-10. Ceramic capacitors with X7R dielectricum are required. Table A-10. Voltage Regulator — Capacitive Loads Num Characteristic 1 VDD external capacitive load 2 VDDPLL external capacitive load A.3 A.3.
PAGE 584
Appendix A Electrical Characteristics A.3.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.3.1.
PAGE 585
Appendix A Electrical Characteristics A.3.2 Oscillator The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail.
PAGE 586
Appendix A Electrical Characteristics A.3.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.3.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL R Cs XFC Pin Phase fosc fref 1 ∆ refdv+1 VCO fvco KΦ fcmp KV Detector Loop Divider 1 1 synr+1 2 Figure A-2.
PAGE 587
Appendix A Electrical Characteristics The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response. f f 2⋅ζ⋅f ref ref 1 < ------------------------------------------- ⋅ ------ → f < -------------- ;( ζ = 0.
PAGE 588
Appendix A Electrical Characteristics 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-3. Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
PAGE 589
Appendix A Electrical Characteristics Table A-13. PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P 2 Symbol Min Typ Max Unit Self Clock Mode frequency fSCM 1 — 5.5 MHz D VCO locking range fVCO 8 — 50 MHz 3 D Lock Detector transition from Acquisition to Tracking mode |∆trk| 3 — 4 %1 4 D Lock Detection |∆Lock| 0 — 1.5 %1 5 D Un-Lock Detection |∆unl| 0.5 — 2.
PAGE 590
Appendix A Electrical Characteristics A.4 A.4.1 Flash NVM NVM Timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum.
PAGE 591
Appendix A Electrical Characteristics A.4.1.4 Mass Erase Erasing a NVM block takes: t mass 1 ≈ 20000 ⋅ ------------------------f NVMOP The setup times can be ignored for this operation. A.4.1.5 Blank Check The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ≈ location ⋅ t cyc + 10 ⋅ t cyc Table A-14.
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Appendix A Electrical Characteristics A.4.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table A-15.
PAGE 593
Appendix A Electrical Characteristics A.5 SPI Characteristics This section provides electrical parametrics and ratings for the SPI. In Table A-16 the measurement conditions are listed. Table A-16. Measurement Conditions Description Value Drive mode full drive mode — 50 pF (20% / 80%) VDDX V Load capacitance CLOAD, on all outputs Thresholds for delay measurement points A.5.1 Unit Master Mode In Figure A-5 the timing diagram for master mode with transmission format CPHA=0 is depicted.
PAGE 594
Appendix A Electrical Characteristics In Figure A-6 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS1 (OUTPUT) 1 2 12 13 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 11 9 MOSI (OUTPUT) PORT DATA LSB IN MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6.
PAGE 595
Appendix A Electrical Characteristics A.5.2 Slave Mode In Figure A-7 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. SS (INPUT) 1 12 13 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 10 8 7 9 MISO (OUTPUT) see note SLAVE MSB 5 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 MOSI (INPUT) BIT 6 . . . 1 MSB IN LSB IN NOTE: Not defined! Figure A-7.
PAGE 596
Appendix A Electrical Characteristics In Table A-18 the timing characteristics for slave mode are listed. Table A-18.
PAGE 597
Appendix A Electrical Characteristics A.6 ATD Characteristics This section describes the characteristics of the analog to digital converter. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test. A.6.1 ATD Operating Characteristics — 5V Range The Table A-19 shows conditions under which the ATD operates.
PAGE 598
Appendix A Electrical Characteristics Table A-20. 3.3V ATD Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10% Num C 1 Rating Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 — — VDDA/2 VDDA V V D Reference Potential Low High 2 C Differential Reference Voltage VRH-VRL 3.0 3.3 3.6 V 3 D ATD Clock Frequency fATDCLK 0.5 — 2.0 MHz 4 D ATD 10-Bit Conversion Period NCONV10 TCONV10 TCONV10 14 7 3.
PAGE 599
Appendix A Electrical Characteristics 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel.
PAGE 600
Appendix A Electrical Characteristics A.6.5 ATD Accuracy — 3.3V Range Table A-23 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-23. 3.3V ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV fATDCLK = 2.0MHz Num C Symbol Min Typ Max Unit 3.25 — mV 1.
PAGE 601
Appendix A Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi 0x3FF 8-Bit Absolute Error Boundary 0x3FE 0x3FD 0x3FC 0xFF 0x3FB 0x3FA 0x3F9 0x3F8 0xFE 0x3F7 0x3F6 0x3F5 0xFD 10-Bit Resolution 0x3F3 9 Ideal Transfer Curve 8 2 8-Bit Resolution 0x3F4 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 50 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-9.
PAGE 602
Appendix A Electrical Characteristics A.7 DAC Characteristics This section describes the characteristics of the digital to analog converter. A.7.1 DAC Operating Characteristics Table A-24. DAC Electrical Characteristics (Operating) Num C Characteristic 1 D DAC Supply 2 D DAC Supply Current Condition D 3 D Reference Potential D 4 D Reference Supply Current 5 D Input Current, Channel Off1 6 D Operating Temperature Range Symbol Min Typ Max Unit VDDA 2.97 — 5.
PAGE 603
Appendix A Electrical Characteristics 1, 2 3 4 ECLK PE4 5 9 Addr/Data (read) PA, PB 6 16 15 10 data addr data 7 8 12 Addr/Data (write) PA, PB data 14 13 data addr 17 11 19 18 Non-Multiplexed Addresses PK5:0 20 21 22 23 ECS PK7 24 25 26 27 28 29 30 31 32 33 34 R/W PE2 LSTRB PE3 NOACC PE7 35 36 IPIPO0 IPIPO1, PE6,5 Figure A-10. General External Bus Timing MC9S12E256 Data Sheet, Rev. 1.
PAGE 604
Appendix A Electrical Characteristics Table A-26. Expanded Bus Timing Characteristics (5V Range) Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF 1 Num C Rating 1 P Frequency of operation (E-clock) 2 P Cycle time 3 D Pulse width, E low high1 Symbol Min Typ Max Unit fo 0 — 25.
PAGE 605
Appendix A Electrical Characteristics Table A-27. Expanded Bus Timing Characteristics (3.3V Range) Conditions are VDDX=3.3V+/-10%, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF 1 Num C Rating 1 P Frequency of operation (E-clock) 2 P Cycle time 3 D Pulse width, E low high1 Symbol Min Typ Max Unit fo 0 — 16.0 MHz tcyc 62.
PAGE 606
Appendix B Ordering Information and Mechanical Drawings Package Options FU = 80 QFP PV = 112 LQFP MC9S12 E256 C FU Package Option Temperature Option Temperature Options C = –40˚C to 85˚C V = –40˚C to 105˚C M = –40˚C to 125˚C Device Title Controller Family Figure B-1. Order Part Number Coding Table B-1 lists the part number coding based on the package and temperature. Table B-1.
PAGE 607
Appendix B Ordering Information and Mechanical Drawings MC9S12E256 Data Sheet, Rev. 1.
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Appendix B Ordering Information and Mechanical Drawings MC9S12E256 Data Sheet, Rev. 1.
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