Datasheet

Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1)
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 101
2.3.2.14 RESERVED3
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.3.2.15 RESERVED4
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.4 Functional Description
2.4.1 Flash Command Operations
Write and read operations are both used for the program, erase, erase verify, and data compress algorithms
described in this subsection. The program and erase algorithms are time controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO)
so that a second command along with the necessary data and address can be stored to the buffer while the
first command remains in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with interrupts generated, if enabled.
Module Base + 0x000E
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-20. RESERVED3
Module Base + 0x000F
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-21. RESERVED4