Datasheet

Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1)
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 103
Figure 2-22. Determination Procedure for PRDIV8 and FDIV Bits
PRDIV8=1
YES
NO
PRDIV8=0 (reset)
FCLK=(PRDCLK)/(1+FDIV[5:0])
PRDCLK=oscillator_clock
PRDCLK=oscillator_clock/8
PRDCLK[MHz]*(5+Tbus[µs])
NO
FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1
YES
START
Tbus < 1µs?
an integer?
FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))
1/FCLK[MHz] + Tbus[µs] > 5
AND
FCLK
> 0.15 MHz
?
END
YES
NO
FDIV[5:0]
> 4?
ALL COMMANDS IMPOSSIBLE
YES
NO
ALL COMMANDS IMPOSSIBLE
NO
TRY TO DECREASE Tbus
YES
OSCILLATOR
CLOCK
> 12.8 MHZ?