Datasheet

Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1)
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 109
Data Compress Operation
The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature
based on selected Flash array data. The final signature, which is stored in the associated banked FDATA
register, is based on the following logic equation which is executed on every data compression cycle during
the operation:
MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn. 2-1
where MISR is the content of the internal signature register associated with each Flash block and DATA
is the data to be compressed as shown in Figure 2-25.
Figure 2-25. 16-Bit MISR Diagram
During the data compress operation, the following steps are executed:
1. MISR is reset to 0xFFFF.
2. DATA from the selected Flash array data range is read and compressed into the MISR with address
incrementing.
3. DATA from the selected Flash array data range is read and compressed into the MISR with address
decrementing.
4. The contents of the MISR are written to the associated banked FDATA register.
DQ
>
+
+
= Exclusive-OR
DATA[0]
M0
DQ
>
+
DATA[1]
M1
DQ
>
+
DATA[2]
M2
DQ
>
+
DATA[3]
M3
DQ
>
+
DATA[4]
M4
DQ
>
+
DATA[5]
M5
DQ
>
+
DATA[15]
M15
...
+ +
+
MISR[15:0] = Q[15:0]