Datasheet

Chapter 2 256 Kbyte Flash Module (S12FTS256K2V1)

MC9S12E256 Data Sheet, Rev. 1.10

Freescale Semiconductor 119

NOTE

Vector addresses and their relative interrupt priority are determined at the

MCU level.

2.8.1 Description of Flash Interrupt Operation

The logic used for generating interrupts is shown in Figure 2-30.

The Flash module uses the CBEIF and CCIF ﬂags in combination with the CBIE and CCIE enable bits to

generate the Flash command interrupt request.

Figure 2-30. Flash Interrupt Implementation

For a detailed description of the register bits, refer to Section 2.3.2.4, “Flash Conﬁguration Register

(FCNFG)” and Section 2.3.2.7, “Flash Status Register (FSTAT)”.

Table 2-22. Flash Interrupt Sources

Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask

Flash address, data and command buffers empty CBEIF (FSTAT register) CBEIE (FCNFG register) I Bit

All Flash commands completed CCIF (FSTAT register) CCIE (FCNFG register) I Bit

Block 0 CBEIF

Flash Command

Block 0 Select

CBEIE

Block 1 CBEIF

Block 1 Select

Block 0 CCIF

Block 0 Select

CCIE

Block 1 CCIF

Block 1 Select

Interrupt Request