Datasheet

Chapter 3 Port Integration Module (PIM9E256V1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
150 Freescale Semiconductor
3.3.5 Port S
Port S is associated with the serial peripheral interface (SPI) and serial communication interfaces (SCI0
and SCI1). Each pin is assigned to these modules according to the following priority: SPI/SCI1/SCI0 >
general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become
SS, SCK, MOSI, and MISO respectively. Refer to the
SPI block description chapter for information on enabling and disabling the SPI.
When the SCI1 receiver and transmitter are enabled, the PS[3:2] pins become TXD1 and RXD1
respectively. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and
RXD0 respectively. Refer to the SCI block description chapter for information on enabling and disabling
the SCI receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
3.3.5.1 Port S I/O Register (PTS)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
3.3.5.2 Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect.
Module Base + 0x0008
76543210
R
PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
SPI:
SS SCK MOSI MISO
SCI1/SCI0
:
TXD1 RXD1 TXD0 RXD0
Reset 00000000
Figure 3-29. Port S I/O Register (PTS)
Module Base + 0x0009
76543210
R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
Reset u u u uuuuu
= Reserved or Unimplemented u = Unaffected by reset
Figure 3-30. Port S Input Register (PTIS)