Datasheet

Chapter 8 Serial Communication Interface (SCIV4) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 251
8.2.3.2 Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
• If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
8.2.3.3 Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes after an
external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or
reception in progress and resets the SCI.
8.2.4 Block Diagram
Figure 8-1 is a high level block diagram of the SCI module, showing the interaction of various function
blocks.