Datasheet

Chapter 10 Inter-Integrated Circuit (IICV2) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
320 Freescale Semiconductor
Figure 10-9. IIC-Bus Transmission Signals
10.4.1.1 START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in Figure 10-9, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
Figure 10-10. Start and Stop Conditions
SCL
SDA
Start
Signal
Ack
Bit
12345678
MSB LSB
12345678
MSB LSB
Stop
Signal
No
SCL
SDA
1234567 8
MSB LSB
1 2 5 678
MSB LSB
Repeated
34
99
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Calling Address Read/ Data Byte
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write
SDA
SCL
START Condition STOP Condition