Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module

MC9S12E256 Data Sheet, Rev. 1.10

330 Freescale Semiconductor

• Edge-aligned or center-aligned PWM signals

• Half-cycle reload capability

• Integral reload rates from 1 to 16

• Individual software-controlled PWM output

• Programmable fault protection

• Polarity control

11.1.2 Modes of Operation

Care must be exercised when using this module in the modes listed in Table 11-2. PWM outputs are placed

in their inactive states in STOP mode, and optionally under WAIT and FREEZE modes. PWM outputs will

be reactivated (assuming they were active to begin with) when these modes are exited

11.1.3 Block Diagrams

Figure 11-1 provides an overview of the PMF module.

The Mux/Swap/Current Sense block is tightly integrated with the dead time insertion block. This detail is

shown in Figure 11-2.

NOTE

It is possible to have both channels of a complementary pair to be high. For

example, if the TOPNEGA (negative polarity for PWM0), BOTNEGA

(negative polarity for PWM1), MASK0 and MASK1 bits are set, both the

PWM complementary outputs of generator A will be high. See

Section 11.3.2.2, “PMF Conﬁgure 1 Register (PMFCFG1)” for the

description of TOPNEG and BOTNEG bits, and Section 11.3.2.3, “PMF

Conﬁgure 2 Register (PMFCFG2)” for the description of the MSK0 and

MSK1 bits.

Table 11-2. Modes When PWM Operation is Restricted

Mode Description

STOP PWM outputs are disabled

WAIT PWM outputs are disabled as a function of the PMFWAI bit.

FREEZE PWM outputs are disabled as a function of the PMFFRZ bit.