Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
336 Freescale Semiconductor
11.3.2 Register Descriptions
The address of a register is the sum of a base address and an address offset. The base address is defined at
the chip level and the address offset is defined at the module level.
11.3.2.1 PMF Configure 0 Register (PMFCFG0)
Read anytime. See bit description for write conditions.
$0032 PMFCNTC
R 0 PMFCNTC
W
$0033 PMFCNTC
R PMFCNTC
W
$0034 PMFMODC
R0
PMFMODC
W
$0035 PMFMODC
R
PMFMODC
W
$0036 PMFDTMC
R0 0 0 0
PMFDTMC
W
$0037 PMFDTMC
R
PMFDTMC
W
$0038–
$003F
Reserved
R
W
Address: $0000
76543210
R
WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA
W
Reset 0 0 0 00000
Figure 11-4. PMF Configure 0 Register (PMFCFG0)
Table 11-3. PMFCFG0 Field Descriptions
Field Description
7
WP
Write Protect — This bit enables write protection to be used for all write-protectable registers. While clear, WP
allows write-protected registers to be written. When set, WP prevents any further writes to write-protected
registers. Once set, WP can be cleared only by reset.
0 Write-protectable registers may be written.
1 Write-protectable registers are write-protected.
Address Name Bit 7 6 54321Bit 0
= Unimplemented or Reserved
Figure 11-3. Quick Reference to PMF Registers (Sheet 4 of 4)