Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
342 Freescale Semiconductor
11.3.2.9 PMF Disable Mapping Registers
Read anytime. These registers cannot be modified after the WP bit is set.
The fault decoder disables PWM pins selected by the fault logic and the disable mapping registers. See
Figure 11-15. Each bank of four bits in the disable mapping registers control the mapping of a single PWM
pin. Refer to Table 11-12.
Table 11-10. PMFQSMP Field Descriptions
Field Description
7–0
QSMP[3:0]
Fault x Qualifying Samples — This field indicates the number of consecutive samples taken at the FAULTx pin
to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault is
present and each sample after that is taken every four bus cycles. See Table 11-11.
where x is 0, 1, 2 and 3
Table 11-11. Qualifying Samples
QSMPx Number of Samples
00 1 sample
(1)
1. There is an asynchronous path from fault pin to disable PWMs
immediately but the fault is qualified in two bus cycles.
01 5 samples
10 10 samples
11 15 samples
Address: $0008
76543210
R
DMP13 DMP12 DMP11 DMP10 DMP03 DMP02 DMP01 DMP00
W
Reset 0 0 0 00000
Figure 11-12. PMF Disable Mapping A Register (PMFDMPA)
Address: $0009
76543210
R
DMP33 DMP32 DMP31 DMP30 DMP23 DMP22 DMP21 DMP20
W
Reset 0 0 0 00000
Figure 11-13. PMF Disable Mapping B Register (PMFDMPB)
Address: $000A
76543210
R
DMP53 DMP52 DMP51 DMP50 DMP43 DMP42 DMP41 DMP53
W
Reset 0 0 0 00000
Figure 11-14. PMF Disable Mapping C Register (PMFDMPC)