Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 345
11.3.2.13 PMF Correction Control Register (PMFCCTL)
Read and write anytime.
Table 11-16. PMFDTMS Field Descriptions
Field Description
5–0
DT[5:0}
DTx Bits — The DTx bits are grouped in pairs, DT0 and DT1, DT2 and DT3, DT4 and DT5. Each pair reflects
the corresponding
ISx pin value as sampled at the end of deadtime.
Address: $000F
76543210
R0 0
ISENS
0
IPOLC IPOLB IPOLA
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 11-19. PMF Correction Control Register (PMFCCTL)
Table 11-17. PMFCCTL Field Descriptions
Field Description
5–4
ISENS
Current Status Sensing Method — This field selects the top/bottom correction scheme, illustrated in Table 11-
18.
Note: Assume the user will provide current sensing circuitry causing the voltage at the corresponding input pin
to be low for positive current and high for negative current. In addition, it assumes the top PWMs are PWM
0, 2, and 4 while the bottom PWMs are PWM 1, 3, and 5.
Note: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM
cycle.
2
IPOLC
Current Polarity — This buffered bit selects the PMF Value register for the PWM4 and PWM5 pins in top/bottom
software correction in complementary mode.
0 PMF Value 4 register in next PWM cycle.
1 PMF Value 5 register in next PWM cycle.
1
IPOLB
Current Polarity — This buffered bit selects the PMF Value register for the PWM2 and PWM3 pins in top/bottom
software correction in complementary mode.
0 PMF Value 2 register in next PWM cycle.
1 PMF Value 3 register in next PWM cycle.
0
IPOLA
Current Polarity — This buffered bit selects the PMF Value register for the PWM0 and PWM1 pins in top/bottom
software correction in complementary mode.
0 PMF Value 0 register in next PWM cycle.
1 PMF Value 1 register in next PWM cycle.
Table 11-18. Correction Method Selection
ISENS Correction Method
00 No correction
(1)
01 Manual correction
10 Current status sample correction on pins
IS0, IS1, and IS2 during deadtime
(2)