Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
352 Freescale Semiconductor
11.3.2.24 PMF Deadtime A Register (PMFDTMA)
Read anytime. This register cannot be modified after the WP bit is set.
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel
operation. A reset sets the PWM deadtime register to a default value of 0x0FFF, selecting a deadtime of
4096-PWM clock cycles minus one bus clock cycle.
NOTE
Deadtime is affected by changes to the prescaler value. The deadtime
duration is determined as follows: DT = P × PMFDTMA – 1, where DT is
deadtime, P is the prescaler value, PMFDTMA is the programmed value of
dead time. For example: if the prescaler is programmed for a divide-by-two
and the PMFDTMA is set to five, then P = 2 and the deadtime value is equal
to DT = 2 × 5 – 1 = 9 IPbus clock cycles. A special case exists when the
P = 1, then DT = PMFDTMA.
11.3.2.25 PMF Enable Control B Register (PMFENCB)
Read anytime and write only if MTG is set.
Address: $0026
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0 0 0
PMFDTMA
W
Reset 0 0 0 0 1 1 1 1 1 1111111
= Unimplemented or Reserved
Figure 11-30. PMF Deadtime A Register (PMFDTMA)
Address: $0028
76543210
R
PWMENB
00000
LDOKB PWMRIEB
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 11-31. PMF Enable Control B Register (PMFENCB)
Table 11-29. PMFENCB Field Descriptions
Field Description
7
PWMENB
PWM Generator B Enable — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit when set enables the PWM generator B and the PWM2 and PWM3 pins. When PWMENB
is clear, PWM generator B is disabled, and the PWM2 and PWM3 pins are in their inactive states unless the
OUTCTL2 and OUTCTL3 bits are set.
0 PWM generator B and PWM2–3 pins disabled unless the respective OUTCTL bit is set.
1 PWM generator B and PWM2–3 pins enabled.