Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
360 Freescale Semiconductor
11.4.3.1 Alignment
Each edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs.
Figure 11-41. Center-Aligned PWM Output
Figure 11-42. Edge-Aligned PWM Output
NOTE
Because of the equals-comparator architecture of this PMF, the modulus
equals zero case is considered illegal. Therefore, the modulus register does
not return to zero, and a modulus value of zero will result in waveforms
inconsistent with the other modulus waveforms. If a modulus of zero is
loaded, the counter will continually count down from $7FFF. This operation
will not be tested or guaranteed. Consider it illegal. However, the dead-time
constraints and fault conditions will still be guaranteed.
11.4.3.2 Period
A PWM period is determined by the value written to the PWM counter modulo register.
The PWM counter is an up/down counter in a center-aligned operation. In this mode the PWM highest
output resolution is two bus clock cycles.
PWM period = (PWM modulus) × (PWM clock period) × 2
UP/DOWN COUNTER
MODULUS = 4
ALIGNMENT REFERENCE
PWM OUTPUT
DUTY CYCLE = 50%
UP COUNTER
MODULUS = 4
ALIGNMENT REFERENCE
PWM OUTPUT
DUTY CYCLE = 50%