Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 363
Writing a logic zero to a INDEPx bit configures the PWM output as a pair of complementary channels.
The PWM pins are paired as shown in Figure 11-47 in complementary channel operation.
Figure 11-47. Complementary Channel Pairs
The complementary channel operation is for driving top and bottom transistors in a motor drive circuit,
such as the one in Figure 11-48.
Figure 11-48. Typical 3 Phase AC Motor Drive
In complementary channel operation, there are three additional features:
• Deadtime insertion
• Separate top and bottom pulse width correction for distortions are caused by deadtime inserted and
the motor drive characteristics
• Separate top and bottom output polarity control
PWM CHANNELS 0 AND 1
PMFVAL1
PWM CHANNELS 2 AND 3
PWM CHANNELS 4 AND 5
REGISTER
TOP
BOTTOM
TOP
BOTTOM
TOP
BOTTOM
PMFVAL0
REGISTER
PMFVAL3
REGISTER
PMFVAL2
REGISTER
PMFVAL5
REGISTER
PMFVAL4
REGISTER
PAIR A
PAIR B
PAIR C
PWM
0
PWM
2
AC
INPUTS
TO
MOTOR
PWM
4
PWM
3
PWM
5
PWM
1