Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 371
Figure 11-57. Internal Correction Logic when ISENS = 10
Figure 11-58. Internal Correction Logic when ISENS = 11
NOTE
Values latched on the
ISx pins are buffered so only one PWM register is
used per PWM cycle. If a current status changes during a PWM period, the
new value does not take effect until the next PWM period.
When initially enabled by setting the PWMEN bit, no current status has previously been sampled. PWM
value registers one, three, and five initially control the three PWM pairs when configured for current status
correction.
Figure 11-59. Correction with Positive Current
DQ
CLK
PWM CONTROLLED BY
PWM CONTROLLED BY
DEADTIME
GENERATOR
DQ
CLK
ISx PIN
A/B
A
B
PWM CYCLE START
TOP PWM
BOTTOM PWM
INITIAL VALUE = 0
ODD PWMVAL REGISTER
EVEN PWMVAL REGISTER
IN DEADTIME
DQ
CLK
PWM CONTROLLED BY
PWM CONTROLLED BY
DEADTIME
GENERATOR
DQ
CLK
ISx PIN
A/B
A
B
PWM CYCLE START
TOP PWM
BOTTOM PWM
INITIAL VALUE = 0
ODD PWMVAL REGISTER
EVEN PWMVAL REGISTER
PMFCNT = PMFMOD
DESIRED LOAD VOLTAGE
BOTTOM PWM
LOAD VOLTAGE
TOP PWM