Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
376 Freescale Semiconductor
NOTE
Loading a new modulus on a half cycle will force the count to the new
modulus value minus one on the next clock cycle. Half cycle reloads are
possible only in center-aligned mode. Enabling or disabling half-cycle
reloads in edge-aligned mode will have no effect on the reload rate.
Figure 11-65. Full Cycle Reload Frequency Change
Figure 11-66. Half Cycle Reload Frequency Change
11.4.7.3 Reload Flag
With a reload opportunity, regardless an actual reload occurs as determined by LDOK bit, the PWMF
reload flag is set. If the PWM reload interrupt enable bit, PWMRIE is set, the PWMF flag generates
CPU interrupt requests allowing software to calculate new PWM parameters in real time. When
PWMRIE is not set, reloads still occur at the selected reload rate without generating CPU interrupt
requests.
Figure 11-67. PWMRF Reload Interrupt Request
RELOAD
CHANGE
UP/DOWN
TO EVERY
TWO OPPORTUNITIES
TO EVERY
OPPORTUNITY
COUNTER
RELOAD
FREQUENCY
TO EVERY
FOUR OPPORTUNITIES
RELOAD
CHANGE
UP/DOWN
TO EVERY
TWO OPPORTUNITIES
TO EVERY
OPPORTUNITY
COUNTER
RELOAD
FREQUENCY
TO EVERY
TWO OPPORTUNITIES
TO EVERY
FOUR OPPORTUNITIES
V
DD
CPU INTERRUPT
PWM RELOAD
REQUEST
DQ
CLK
CLR
READ PWMRF AS 1 THEN
WRITE 0 TO PWMF
RESET
PWMRF
PWMRIE