Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 381
11, the PWMs are enabled when the next PWM half cycle begins regardless of the state of the logic
level detected by the filter at the fault. See Figure 11-77 and Figure 11-78.
• PWM pins disabled by the FAULT1 pin or the FAULT3 pin are enabled when
— Software clears the corresponding FFLAGx flag
— The filter detects a logic zero on the fault pin at the start of the next PWM half cycle boundary.
See Figure 11-79.
Figure 11-77. Manual Fault Clearing (Faults 0 and 2) — QSMP = 00
Figure 11-78. Manual Fault Clearing (Faults 0 and 2) — QSMP = 01, 10, or 11
Figure 11-79. Manual Fault Clearing (Faults 1 and 3)
NOTE
PWM half-cycle boundaries occur at both the PWM cycle start and when the
counter equals the modulus, so in edge-aligned operation full-cycles and
half-cycles are equal.
PWMS ENABLED
FAULT0 OR
FAULT2
PWMS ENABLED
PWMS DISABLED
FFLAGx CLEARED
PWMS ENABLED
FAULT0 OR
FAULT2
PWMS ENABLED
PWMS DISABLED
FFLAGx CLEARED
PWMS ENABLED
FAULT1 OR
FAULT3
PWMS ENABLED PWMS DISABLED
FFLAGx CLEARED