Datasheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12E256 Data Sheet, Rev. 1.10
382 Freescale Semiconductor
NOTE
Fault protection also applies during software output control when the
OUTCTLx bits are set. Fault clearing still occurs at half PWM cycle
boundaries while the PWM generator is engaged, PWMEN equals one. But
the OUTx bits can control the PWM pins while the PWM generator is off,
PWMEN equals zero. Thus, fault clearing occurs at IPbus cycles while the
PWM generator is off and at the start of PWM cycles when the generator is
engaged.
11.5 Resets
All PWM registers are reset to their default values upon any system reset.
11.6 Clocks
The system bus clock is the only clock required by this module.
11.7 Interrupts
Seven PWM sources can generate CPU interrupt requests:
• Reload flag x (PWMRFx)—PWMRFx is set at the beginning of every PWM Generator x reload
cycle. The reload interrupt enable bit, PWMRIEx, enables PWMRFx to generate CPU interrupt
requests.
where x is A, B and C.
• Fault flag x (FFLAGx)—The FFLAGx bit is set when a logic one occurs on the FAULTx pin. The
fault pin interrupt enable x bit, FIEx, enables the FFLAGx flag to generate CPU interrupt requests.
where x is 0, 1, 2 and 3.
11.8 Electrical Specifications
In general, electrical specifications may vary a bit from chip to chip. This section illustrates typical
parameters. Refer to the chip specification electrical and timing specifications for details of a specific
implementation.
Table 11-41. DC Electrical Characteristics
Characteristic Symbol Min Typ Max Unit
Input high voltage V
IH
2.0 — 5.5 V
Input low voltage V
IL
–0.3 — 0.8 V
Input hysteresis on Schmitt trigger inputs (Fault pins) V
HYS
— 0.3 — V
Input pullup current I
PU
–50 –100 –170 µA
Input current low (pullups disabled) I
IL
–10 — 10 µA
Input current high (pullups disabled) I
IH
–10 — 10 µA
Output tri-state current low I
OZL
–10 — 10 µA