Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 427
13.3.3.3 Output Compare 7 Mask Register (OC7M)
Read or write anytime.
13.3.3.4 Output Compare 7 Data Register (OC7D)
Read or write anytime.
Module Base + 0x0002
76543210
R
OC7M7 OC7M6 OC7M5 OC7M4
0000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-5. Output Compare 7 Mask Register (OC7M)
Table 13-3. OC7M Field Descriptions
Field Description
7–4
OC7M[7:4]
Output Compare 7 Mask "n" Channel Bits — Setting the OC7Mn (n ranges from 4 to 6) will set the
corresponding port to be an output port when the corresponding TIOSn (n ranges from 4 to 6) bit is set to be an
output compare.
0 Does not set the corresponding port to be an output port
1 Sets the corresponding port to be an output port when this corresponding TIOS bit is set to be an output
compare
Note: A successful channel 7 output compare overrides any channel 6:4 compares.For each OC7M bit that is
set, the output compare action reflects the corresponding OC7D bit.
Module Base + 0x0003
76543210
R
OC7D7 OC7D6 OC7D5 OC7D4
0000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-6. Output Compare 7 Data Register (OC7D)
Table 13-4. OC7D Field Descriptions
Field Description
7–4
OC7D[7:4]
Output Compare 7 Data for Channel "n" — A channel 7 output compare will cause bits in the output compare
7 data register to transfer to the timer port data register if the corresponding output compare 7 mask register bits
are set.