Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
428 Freescale Semiconductor
13.3.3.5 Timer Count Register (TCNT)
Read anytime. Writable only in special mode (refer for SOC guide for special modes).
The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock
cycle. A separate read/write for high byte and low byte will give a different result than accessing them as
a word. The period of the first count after a write to the TCNT registers may be a different length because
the write is not synchronized with the prescaler clock.
13.3.3.6 Timer System Control Register 1 (TSCR1)
Read or write anytime.
Module Base + 0x0004–0x0005
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
tcnt
15
tcnt
14
tcnt
13
tcnt
12
tcnt
11
tcnt
10
tcnt
9
tcnt
8
tcnt
7
tcnt
6
tcnt
5
tcnt
4
tcnt
3
tcnt
2
tcnt
1
tcnt
0
W
Reset 0 0 0 0 0 0 0 0 0 0000000
Figure 13-7. Timer Count Register (TCNT)
Module Base + 0x0006
76543210
R
TEN TSWAI TSFRZ TFFCA
0000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-8. Timer System Control Register 1 (TSCR1)
Table 13-5. TSCR1 Field Descriptions
Field Description
7
TEN
Timer Enable — If for any reason the timer is not active, there is no divide by 64 clock for the pulse accumulator
since the divide by 64 clock is generated by the timer prescaler.
0 Disables the timer. (Used for reducing power consumption).
1 Enables the timer.
6
TSWAI
Timer Module Stops While in Wait
0 Allows the timer and the pulse accumulator to continue running during the wait1 mode.
1 Disables the timer and pulse accumulator when the MCU is in the wait mode. Timer interrupts cannot be used
to get the MCU out of wait mode.
5
TSFRZ
Timer Stops While in Freeze Mode — TSFRZ does not stop the pulse accumulator.
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.