Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 429
13.3.3.7 Timer Toggle On Overflow Register 1 (TTOV)
Read or write anytime.
4
TFFCA
Timer Fast Flag Clear All
0 Allows the timer flag clearing.
1 For TFLG1 register, a read from an input capture or a write to the output compare channel [TC 7:4] causes
the corresponding channel flag, CnF, to be cleared.For TFLG2 register, any access to the TCNT register clears
the TOF flag. Any access to the PACNT registers clears the PAOVF and PAIF bits in the PAFLG register. This
has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to
avoid accidental flag clearing due to unintended accesses.
Module Base + 0x0007
76543210
R
TOV7 TOV6 TOV5 TOV4
0000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-9. Timer Toggle On Overflow Register 1 (TTOV)
Table 13-6. TTOV Field Descriptions
Field Description
7–4
TOV[7:4]
Toggle On Overflow Bits — TOVn toggles output compare pin on overflow. This feature only takes effect when
the corresponding channel is configured for an output compare mode. When set, an overflow toggle on the output
compare pin takes precedence over forced output compare but not channel 7 override events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
Table 13-5. TSCR1 Field Descriptions (continued)
Field Description