Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
432 Freescale Semiconductor
13.3.3.9 Timer Control Register 3 (TCTL3)
Read or write anytime.
13.3.3.10 Timer Interrupt Enable Register (TIE)
Read or write anytime.
Module Base + 0x000A
76543210
R
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
W
Reset 0 0 0 00000
Figure 13-11. Timer Control Register 3 (TCTL3)
Table 13-10. TCTL3 Field Descriptions
Field Description
7, 5, 3, 1
EDG[7:4]B
6, 4, 2, 0
EDG[7:4]A
Input Capture Edge Control — These four pairs of control bits configure the input capture edge detector
circuits. See Table 13-11.
Table 13-11. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)
Module Base + 0x000C
76543210
R
C7I C6I C5I C4I
0000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-12. Timer Interrupt Enable Register (TIE)
Table 13-12. TIE Field Descriptions
Field Description
7–4
C[7:4]I
Input Capture/Output Compare Interrupt Enable.
0 Disables corresponding Interrupt flag (CnF of TFLG1 register) from causing a hardware interrupt
1 Enables corresponding Interrupt flag (CnF of TFLG1 register) to cause a hardware interrupt