Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 433
13.3.3.11 Timer System Control Register 2 (TSCR2)
Read or write anytime.
Module Base + 0x000D
76543210
R
TOI
000
TCRE PR2 PR1 PR0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-13. Timer System Control Register 2 (TSCR2)
Table 13-13. TSCR2 Field Descriptions
Field Description
7
TOI
Timer Overflow Interrupt Enable
0 Hardware Interrupt request inhibited.
1 Hardware interrupt requested when TOF flag set in TFLG2 register.
3
TCRE
Timer Counter Reset Enable — This mode of operation is similar to an up-counting modulus counter.
If register TC7 = $0000 and TCRE = 1, the timer counter register (TCNT) will stay at $0000 continuously. If
register TC7 = $FFFF and TCRE = 1, TOF will not be set when the timer counter register (TCNT) is reset from
$FFFF to $0000.
TCRE=1 and TC7!=0,the TCNT cycle period will be TC7 x "prescaler counter width"+"1
Bus Clock",for a more detail explanation please refer to (1.4.4 Output Compare
).
0 Inhibits Timer Counter reset and counter continues to run.
1 Enables Timer Counter reset by a successful output compare on channel 7
2–0
PR[2:0]
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 13-14.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
Table 13-14. Timer Clock Selection
PR2 PR1 PR0 Timer Clock
0 0 0 Bus Clock / 1
0 0 1 Bus Clock / 2
0 1 0 Bus Clock / 4
0 1 1 Bus Clock / 8
1 0 0 Bus Clock / 16
1 0 1 Bus Clock / 32
1 1 0 Bus Clock / 64
1 1 1 Bus Clock / 128