Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
434 Freescale Semiconductor
13.3.3.12 Main Timer Interrupt Flag 1 (TFLG1)
Read anytime.
13.3.3.13 Main Timer Interrupt Flag 2 (TFLG2)
Read anytime.
Module Base + 0x000E
76543210
R
C7F C6F C5F C4F
0000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-14. Main Timer Interrupt Flag 1 (TFLG1)
Table 13-15. TFLG1 Field Descriptions
Field Description
7–4
C[7:4]F
Input Capture/Output Compare Channel Flag — These flags are set when an input capture or output compare
event occurs. Flag set on a particular channel is cleared by writing a one to that corresponding CnF bit. Writing
a zero to CnF bit has no effect on its status. When TFFCA bit in TSCR register is set, a read from an input capture
or a write into an output compare channel will cause the corresponding channel flag CnF to be cleared.
0 No event (Input Capture or Output Compare event) occurred.
1 Input Capture or Output Compare event occurred
Module Base + 0x000F
76543210
R
TOF
0000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-15. Main Timer Interrupt Flag 2 (TFLG2)
Table 13-16. TFLG2 Field Descriptions
Field Description
7
TOF
Timer Overflow Flag — The TFLG2 register indicates when an interrupt has occurred. Writing a one to the TOF
bit will clear it. Any access to TCNT will clear TOF bit of TFLG2 register if the TFFCA bit in TSCR register is set.
0 Flag indicates an Interrupt has not occurred.
1 Flag indicates that an Interrupt has occurred (Set when 16-bit free-running timer counter overflows from
$FFFF to $0000)