Datasheet
Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 435
13.3.3.14 Timer Input Capture/Output Compare Registers (TC4–TC7)
Read anytime. Write anytime for output compare function. Writes to these registers have no effect during
input capture.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
NOTE
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
TC4 Module Base + 0x0018–0x0019
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
tc4
15
tc4
14
tc4
13
tc4
12
tc4
11
tc4
10
tc4
9
tc4
8
tc4
7
tc4
6
tc4
5
tc4
4
tc4
3
tc4
2
tc4
1
tc4
0
Reset 0 0 0 0 0 0 0 0 0 0000000
TC5 Module Base + 0x001A–0x001B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
tc5
15
tc5
14
tc5
13
tc5
12
tc5
11
tc5
10
tc5
9
tc5
8
tc5
7
tc5
6
tc5
5
tc5
4
tc5
3
tc5
2
tc5
1
tc5
0
Reset 0 0 0 0 0 0 0 0 0 0000000
TC6 Module Base + 0x001C–0x001D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
tc6
15
tc6
14
tc6
13
tc6
12
tc6
11
tc6
10
tc6
9
tc6
8
tc6
7
tc6
6
tc6
5
tc6
4
tc6
3
tc6
2
tc6
1
tc6
0
Reset 0 0 0 0 0 0 0 0 0 0000000
TC7 Module Base + 0x001E–0x001F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
tc7
15
tc7
14
tc7
13
tc7
12
tc7
11
tc7
10
tc7
9
tc7
8
tc7
7
tc7
6
tc7
5
tc7
4
tc7
3
tc7
2
tc7
1
tc7
0
Reset 0 0 0 0 0 0 0 0 0 0000000
Figure 13-16. Timer Input Capture/Output Compare Registers (TC4–TC7)