Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
436 Freescale Semiconductor
13.3.3.15 16-Bit Pulse Accumulator Control Register (PACTL)
Read: any time
Write: any time
Module Base + 0x0020
76543210
R0
PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 13-17. 16-Bit Pulse Accumulator Control Register (PACTL)
Table 13-17. PACTL Field Descriptions
Field Description
6
PAEN
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled. When PAEN is set, the PACT is enabled.The
PACT shares the input pin with IOC7.
0 Pulse Accumulator system disabled
1 Pulse Accumulator system enabled
5
PAMOD
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
See Table 13-18.
0 Event counter mode
1 Gated time accumulation mode
4
PEDGE
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode).
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since the divide by 64 clock is generated by
the timer prescaler. See Table 13-18.
3–2
CLK[1:0]
Clock Select Bits — For the description of PACLK please refer to Figure 13-22.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input
clock to the timer counter. The change from one selected clock to the other happens immediately after these bits
are written. See Table 13-19.
1
PAOVI
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF bit of PFLG register is set.
0
PAI
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF bit of PAFLG register is set.