Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
438 Freescale Semiconductor
13.3.3.17 Pulse Accumulators Count Registers (PACNT)
Read or write any time.
When PACNT overflows from $FFFF to $0000, the PAOVF bit of PAFLG register is set.
These registers contain the number of active input edges on TOC7 input pin since the last reset. Full count
register access should take place in one clock cycle. A separate read/write for high byte and low byte will
give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an
active edge on the pulse accumulator input pin may miss the last count since
the input has to be synchronized with the bus clock first.
13.4 Functional Description
13.4.1 General
This section provides a complete functional description of the timer S12TIM16B4C block. Please refer to
the detailed timer block diagram in Figure 13-20 as necessary.
Module Base + 0x0022–0x0023
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
pacnt
15
pacnt
14
pacnt
13
pacnt
12
pacnt
11
pacnt
10
pacnt
9
pacnt
8
pacnt
7
pacnt
6
pacnt
5
pacnt
4
pacnt
3
pacnt
2
pacnt
1
pacnt
0
Reset 0 0 0 0 0 0 0 0 0 0000000
Figure 13-19. Pulse Accumulators Count Registers (PACNT)