Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 439
Figure 13-20. Detailed Timer Block Diagram
13.4.2 Prescaler
The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64, or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
PRESCALER
CHANNEL 4
IOC4 PIN
16-BIT COUNTER
LOGIC
PR[2:1:0]
DIVIDE-BY-64
TC4
EDGE
DETECT
PACNT(HI):PACNT(LO)
PAOV F
PEDGE
PAOV I
PAMOD
PAE
16-BIT COMPARATOR
TCNT(HI):TCNT(LO)
16-BIT COUNTER
INTERRUPT
LOGIC
TOF
TOI
C4F
EDGE
DETECT
CXF
CHANNEL7
TC7
16-BIT COMPARATOR C7F
IOC7 PIN
LOGIC
EDGE
DETECT
OM:OL4
TOV4
OM:OL7
TOV7
EDG7A
EDG7B
EDG4B
TCRE
PAI F
CLEAR COUNTER
PAI F
PAI
INTERRUPT
LOGIC
CXI
INTERRUPT
REQUEST
PAOV F
CH. 7 COMPARE
CH.7 CAPTURE
MUX
CLK[1:0]
PACL K
PACLK/256
PACLK/65536
IOC4 PIN
IOC7 PIN
PACL K
PACLK/256
PACLK/65536
TE
CH. 4 COMPARE
CH. 4 CAPTURE
PA INPUT
EDG4A
CHANNEL 7 OUTPUT
COMPARE
IOC4
IOC7
BUS CLOCK
BUS CLOCK
PAOV F
PAOV I
TOF
C4F
C7F