Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
440 Freescale Semiconductor
13.4.3 Input Capture
Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The
input capture function captures the time at which an external event occurs. When an active edge occurs on
the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel
registers, TCn.
The minimum pulse width for the input capture input is greater than two bus clocks.
An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt
requests.
13.4.4 Output Compare
Setting the I/O select bit, IOSn, configures channel n as an output compare channel. The output compare
function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the
timer counter reaches the value in the channel registers of an output compare channel, the timer can set,
clear, or toggle the channel pin. An output compare on channel n sets the CnF flag. The CnI bit enables the
CnF flag to generate interrupt requests.
The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both
OMn and OLn disconnects the pin from the output logic.
Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output
compare does not set the channel flag.
A successful output compare on channel 7 overrides output compares on all other output compare
channels. The output compare 7 mask register masks the bits in the output compare 7 data register. The
timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the timer counter. A
channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse
accumulator input.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is
stored in an internal latch. When the pin becomes available for general-purpose output, the last value
written to the bit appears at the pin.
When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches
TC7 value, it will last only one bus cycle then reset to 0.
Note: in Figure 13-21,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock
Figure 13-21. The TCNT cycle diagram under TCRE=1 condition
TC7
0
1
----- TC7-1 TC7
0
TC7 event
TC7 event
prescaler
counter
1 bus
clock