Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 441
13.4.5 Pulse Accumulator
The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes:
• Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin,
IOC7.
• Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit
selects the mode of operation.
The minimum pulse width for the PAI input is greater than two bus clocks. The maximum input frequency
on the pulse accumulator channel is one half the bus frequency or Eclk.
Figure 13-22. Pulse Accumulator System Block Diagram
13.4.5.1 Event Counter Mode
Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7
pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to
increment the count.
16 BIT CNTR
PA COUNT REG
DATA BUS
PT7
PIN
LOGIC
DIVIDE BY 64
PA CNTRL REGBUS CLOCK
PINPAIF