Datasheet

Chapter 13 Timer (S12TIM16B4CV1) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
444 Freescale Semiconductor
13.6.2 Description of Interrupt Operation
The S12TIM16B4C uses a total of 7 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent. More information on interrupt vector offsets and interrupt numbers can be found in
the System on Chip Guide.
13.6.2.1 Channel [7:4] Interrupt
These active high outputs is asserted by the module to request a timer channel 7 – 4 interrupt following an
input capture or output compare event on these channels [7-4]. For the interrupt to be asserted on a specific
channel, the enable, CnI bit of TIE register should be set. These interrupts are serviced by the system
controller.
13.6.2.2 Pulse Accumulator Input Interrupt
This active high output is asserted by the module to request a timer pulse accumulator input interrupt
following the configured event on IOC7 input pin (in either modes, event mode and time accumulation
mode) when pulse accumulator input interrupt enable, PAI bit in PACTL register is set. This interrupt is
serviced by the system controller.
NOTE
For more information about event mode operation and gated time
accumulation operation of the timers refer to Section 13.4, “Functional
Description”. Further details can be found in creation guide of this module.
13.6.2.3 Pulse Accumulator Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator overflow
interrupt, following the timer pulse accumulator counter overflow, when the pulse accumulator overflow
enable bit, PAOVI of PACTL register is set. This interrupt is serviced by the system controller.
NOTE
For more information about event mode operation and gated time
accumulation operation of the timers refer to Section 13.4, “Functional
Description”. Further details can be found in creation guide of this module.
13.6.2.4 Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt, following the
timer counter overflow when the overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is
serviced by the system controller.