Datasheet

Chapter 19 Module Mapping Control (MMCV4) Block Description
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 559
19.3.2.5 Reserved Test Register 0 (MTST0)
Read: Anytime
Write: No effect — this register location is used for internal test purposes.
19.3.2.6 Reserved Test Register 1 (MTST1)
Read: Anytime
Write: No effect — this register location is used for internal test purposes.
Table 19-6. External Stretch Bit Definition
Stretch Bit EXSTR1 Stretch Bit EXSTR0 Number of E Clocks Stretched
00 0
01 1
10 2
11 3
Module Base + 0x0014
Starting address location affected by INITRG register setting.
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 19-7. Reserved Test Register 0 (MTST0)
Module Base + 0x0017
Starting address location affected by INITRG register setting.
76543210
R00000000
W
Reset 0 0 0 10000
= Unimplemented or Reserved
Figure 19-8. Reserved Test Register 1 (MTST1)