Datasheet

Appendix A Electrical Characteristics
MC9S12E256 Data Sheet, Rev. 1.10
598 Freescale Semiconductor
A.6.3 Factors Influencing Accuracy
Three factors — source resistance, source capacitance and current injection — have an influence on the
accuracy of the ATD.
A.6.3.1 Source Resistance
Due to the input pin leakage current as specified in Table A-6 and Table A-7 in conjunction with the source
resistance there will be a voltage drop from the signal source to the ATD input. The maximum source
resistance R
S
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current.
If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger
values of source resistance are allowed.
A.6.3.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C
f
≥ 1024 * (C
INS
- C
INN
).
A.6.3.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than VRH and 0x000 for values
less than VRL unless the current is higher than specified as disruptive conditions.
Table A-20. 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V
DDA
<= 3.3V+10%
Num C Rating Symbol Min Typ Max Unit
1 D Reference Potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
—
—
V
DDA
/2
V
DDA
V
V
2 C Differential Reference Voltage V
RH
-V
RL
3.0 3.3 3.6 V
3 D ATD Clock Frequency f
ATDCLK
0.5 — 2.0 MHz
4 D ATD 10-Bit Conversion Period
Clock Cycles
1
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
Conv, Time at 4.0MHz
2
ATD Clock f
ATDCLK
1
The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2
Reduced accuracy see Table A-22 and Table A-23.
N
CONV10
T
CONV10
T
CONV10
14
7
3.5
—
—
—
28
14
7
Cycles
µs
µs
5 D ATD 8-Bit Conversion Period
Clock Cycles
1
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV8
T
CONV8
12
6
—
—
26
13
Cycles
µs
6 D Recovery Time (V
DDA
=3.3 Volts) t
REC
——20µs
7 P Reference Supply current I
REF
— — 0.250 mA