Datasheet

Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
MC9S12E256 Data Sheet, Rev. 1.10
Freescale Semiconductor 71
1.5 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-7 shows the clock connections from the CRG to all modules. Consult Chapter 4, “Clocks and
Reset Generator (CRGV4) Block Description” for details on clock generation.
Figure 1-7. Clock Connections
Table 1-6. Clock Selection Based on PE7
PE7 = XCLKS Description
1 Colpitts Oscillator selected
0 Pierce Oscillator/external clock selected
CRG
Bus Clock
Core Clock
EXTAL
XTAL
Oscillator Clock
HCS12 CORE
PWM
RAM
PIM
IIC
DAC
Flash
ATD
SCI0, SCI1, SCI2
PMF
SPI
BDM
OSC
CPU
MEBI MMC
INT DBG
TIM0, TIM1, TIM2
VREG