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HCS12

Microcontrollers

freescale.com

MC9S12E128

MC9S12E64

MC9S12E32

Data Sheet

MC9S12E128V1

Rev. 1.07

10/2005

Summary of content (606 pages)

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MC9S12E128 MC9S12E64 MC9S12E32 Data Sheet HCS12 Microcontrollers MC9S12E128V1 Rev. 1.07 10/2005 freescale.
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MC9S12E128 Data Sheet covers MC9S12E64 & MC9S12E32 MC9S12E128V1 Rev. 1.
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision History Date Revision Level October 10, 2005 01.07 Description New Data Sheet Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) . . . . . . . 21 Chapter 2 128 Kbyte Flash Module (FTS128K1V1) . . . . . . . . . . . . . . . . . . 85 Chapter 3 Port Integration Module (PIM9E128V1). . . . . . . . . . . . . . . . . . 119 Chapter 4 Clocks and Reset Generator (CRGV4) . . . . . . . . . . . . . . . . . . 165 Chapter 5 Oscillator (OSCV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) . . . . . . . . . . .
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MC9S12E128 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.1 1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.
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1.4.28 PQ[6:4] / IS[2:0] — Port Q I/O Pins [6:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.4.29 PQ[3:0] / FAULT[3:0] — Port Q I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.4.30 PS7 / SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.4.31 PS6 / SCK — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.4.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.1 2.2 2.3 2.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.1.
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3.6.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 3.6.3 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Chapter 4 Clocks and Reset Generator (CRGV4) 4.1 4.2 4.3 4.4 4.5 4.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.1.1 Features . . . .
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Chapter 5 Oscillator (OSCV2) 5.1 5.2 5.3 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 External Signal Description . . . . .
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.1 7.2 7.3 7.4 7.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.1.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.1 9.2 9.3 9.4 9.5 9.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.1.
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10.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 10.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 10.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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12.3 12.4 12.5 12.6 12.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.3.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.1.3 Block Diagram . . . . .
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15.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 15.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 15.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 15.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 15.4.
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17.6.2 Highest Priority I-Bit Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.6.3 Interrupt Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.1 Introduction . . . . . . . . . . . . . . . . . .
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Appendix A Electrical Characteristics A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 A.1.3 Pins . . . . . . . . . . . . . . . . . . . .
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MC9S12E128 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) • • • • • • • Two 1-channel Digital-to-Analog Converters (DAC) — 8-bit resolution Analog-to-Digital Converter (ADC) — 16-channel module with 10-bit resolution — External conversion trigger capability Three 4-channel Timers (TIM) — Programmable input capture or output compare channels — Simple PWM mode — Counter modulo reset — External event counting — Gated time accumulation 6 PWM channels (PWM) — Programmable period and duty cycle — 8-bit 6-chann
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) • • • • 1.1.2 Operating frequency — 50MHz equivalent to 25MHz Bus Speed Internal 2.5V Regulator — Input voltage range from 3.135V to 5.5V — Low power mode capability — Includes low voltage reset (LVR) circuitry — Includes low voltage interrupt (LVI) circuitry 112-Pin LQFP or 80-Pin QFP or 64-Pin QFN package — Up to 90 I/O lines with 5V input and drive capability (112 pin package) — Up to two dedicated 5V input only lines (IRQ and XIRQ) — Sixteen 3.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) TIM1 PW10 PW11 PW12 PW13 PW14 PW15 IOC24 IOC25 IOC26 IOC27 Multiplexed Address/Data Bus PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PTB ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DDRB PTA DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DDRA ADC/DAC 3.3V/5V Voltage Reference VRH VRL I/O Driver 3.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.2 Device Memory Map Table 1-1 shows the device register map of the MC9S12E128 after reset. Figure 1-2, Figure 1-3 and Figure 1-4 illustrate the device memory map with Flash and RAM. Table 1-1.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) $0000 $0400 $0000 1K Register Space $03FF Mappable to any 2K Boundary $2000 8K Bytes RAM $3FFF Mappable to any 8K Boundary $4000 0.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) $0000 $0400 $0000 1K Register Space $03FF Mappable to any 2K Boundary $3000 4K Bytes RAM $3FFF Mappable to any 4K Boundary $4000 0.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) $0000 $0400 $0000 1K Register Space $03FF Mappable to any 2K Boundary $3700 2K Bytes RAM $3FFF Mappable to any 2K Boundary $4000 0.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.2.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0010 – 0x0014 MMC Map 1 of 4 (HCS12 Module Mapping Control) Address Name 0x0010 INITRM 0x0011 INITRG 0x0012 INITEE 0x0013 MISC 0x0014 MTST0 R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RAM15 RAM14 RAM13 RAM12 RAM11 REG14 REG13 REG12 REG11 EE15 EE14 EE13 EE12 EE11 0 0 0 0 Bit 7 6 5 0 W R W R Bit 2 Bit 1 0 0 0 0 0 0 EXSTR1 EXSTR0 ROMHM ROMON 4 3 2 1 Bit 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WRINT ADR3 AD
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x001A – 0x001B Miscellaneous Peripherals (Device User Guide) Address Name 0x001A PARTIDH 0x001B PARTIDL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W R W 0x001C – 0x001D MMC Map 3 of 4 (HCS12 Module Mapping Control, Device User Guide) Address Name 0x001C MEMSIZ0 0x001D MEMSIZ1 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reg_s
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0020 – 0x002F DBG (Including BKP) Map 1 of 1 (HCS12 Debug) (continued) Address 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F Name DBGCCH R — W DBGCCL R — W DBGC2 R BKPCT0 W DBGC3 R BKPCT1 W DBGCAX R BKP0X W DBGCAH R BKP0H W DBGCAL R BKP0L W DBGCBX R BKP1X W DBGCBH R BKP1H W DBGCBL R BKP1L W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0034 – 0x003F CRG (Clock and Reset Generator) Address Name 0x0034 SYNR 0x0035 REFDV 0x0036 CTFLG TEST ONLY 0x0037 CRGFLG 0x0038 CRGINT 0x0039 CLKSEL 0x003A PLLCTL 0x003B RTICTL 0x003C COPCTL 0x003D FORBYP TEST ONLY 0x003E CTCTL TEST ONLY 0x003F ARMCOP R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 TOUT7 TOUT6 TOUT5 TOUT4 TOUT
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0040 – 0x006F TIM0 (Timer 16 Bit 4 Channels) (Sheet 2 of 4) Address Name 0x0046 TSCR1 0x0047 TTOV 0x0048 TCTL1 0x0049 Reserved 0x004A TCTL3 0x004B Reserved 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 Reserved 0x0051 Reserved 0x0052 Reserved 0x0053 Reserved 0x0054 Reserved 0x0055 Reserved 0x0056 Reserved 0x0057 Reserved 0x0058 TC4 (hi) R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0040 – 0x006F TIM0 (Timer 16 Bit 4 Channels) (Sheet 3 of 4) Address Name 0x0059 TC4 (lo) 0x005A TC5 (hi) 0x005B TC5 (lo) 0x005C TC6 (hi) 0x005D TC6 (lo) 0x005E TC7 (hi) 0x005F TC7 (lo) 0x0060 PACTL 0x0061 PAFLG 0x0062 PACNT (hi) 0x0063 PACNT (lo) 0x0064 Reserved 0x0065 Reserved 0x0066 Reserved 0x0067 Reserved 0x0068 Reserved 0x0069 Reserved 0x006A Reserved 0x006B Reserved R W R W R W R W R W R W R W R Bit 7 Bi
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0040 – 0x006F TIM0 (Timer 16 Bit 4 Channels) (Sheet 4 of 4) Address Name 0x006C Reserved 0x006D Reserved 0x006E Reserved 0x006F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 W R W R W R W 0x0070 – 0x007F Reserved Address Name 0x0070– 0x007F Re
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0080 – 0x00AF ATD (Analog to Digital Converter 10 Bit 16 Channel) (Sheet 2 of 3) Address Name 0x008B ATDSTAT1 0x008C ATDDIEN0 0x008D ATDDIEN1 0x008E PORTAD0 0x008F PORTAD1 0x0090 ATDDR0H 0x0091 ATDDR0L 0x0092 ATDDR1H 0x0093 ATDDR1L 0x0094 ATDDR2H 0x0095 ATDDR2L 0x0096 ATDDR3H 0x0097 ATDDR3L 0x0098 ATDDR4H 0x0099 ATDDR4L 0x009A ATDDR5H 0x009B ATDDR5L 0x009C ATDDR6H 0x009D ATDDR6L R Bit 7 Bit 6 Bit 5 Bit 4 Bi
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0080 – 0x00AF ATD (Analog to Digital Converter 10 Bit 16 Channel) (Sheet 3 of 3) Address Name 0x009E ATDDR7H 0x009F ATDDR7L 0x00A0 ATDDR8H 0x00A1 ATDDR8L 0x00A2 ATDDR9H 0x00A3 ATDDR9L 0x00A4 ATDDR10H 0x00A5 ATDDR10L 0x00A6 ATDDR11H 0x00A7 ATDDR11L 0x00A8 ATDDR12H 0x00A9 ATDDR12L 0x00AA ATDDR13H 0x00AB ATDDR13L 0x00AC ATDDR14H 0x00AD ATDDR14L 0x00AE ATDDR15H 0x00AF ATDDR15L 1 2 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x00B0 – 0x00C7 Reserved Address Name 0x00B0– 0x00C7 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 W 0x00C8 – 0x00CF SCI0 (Asynchronous Serial Interface) Address Name 0x00C8 SCIBDH 0x00C9 SCIBDL 0x00CA SCICR1 0x00CB SCICR2 0x00CC SCISR1 0x00CD SCISR2 0x00CE SCIDRH 0x00CF SCIDRL 1 R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IREN TNP1 TNP0 SBR12 SBR11
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x00D0 – 0x00D7 SCI1 (Asynchronous Serial Interface) (continued) Address Name 0x00D5 SCISR2 0x00D6 SCIDRH 0x00D7 SCIDRL 1 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 TXPOL1 RXPOL1 BRK13 TXDIR 0 0 0 0 0 0 W R R8 W T8 Bit 0 RAF R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 TXPOL and RXPOL are available in version V04 of SCI 0x00D8 – 0x00DF SPI (Serial Peripheral Interface) Address Name 0x
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x00E0 – 0x00E7 IIC (Inter-IC Bus) (continued) Address Name 0x00E4 IBDR 0x00E5 Reserved 0x00E6 Reserved 0x00E7 Reserved R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W 0x00E8 – 0x00EF SCI2 (Asynchronous Serial Interface) Address Name 0x00E8 SCIBDH 0x00E9 SCIBDL 0x00EA SCICR1 0x00EB SCICR2 0x00EC SCISR1 0
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x00F0 – 0x00F3 DAC0 (Digital-to-Analog Converter) Address Name 0x00F0 DACC0 0x00F1 DACC1 0x00F2 DACD 0x00F3 DACD Bit 7 R W R Bit 6 Bit 5 Bit 4 DACTE 0 0 0 0 0 BIT7 BIT6 BIT7 BIT6 DACE Bit 3 Bit 2 Bit 1 Bit 0 DJM DSGN DACWAI DACOE 0 0 0 0 0 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Bit 3 Bit 2 Bit 1 Bit 0 DJM DSGN DACWAI DACOE W R W R W 0x00F4 – 0x00F7 DAC1 (Digital-to-Analog C
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0100 – 0x010F Flash Control Register (continued) Address Name 0x0105 FSTAT 0x0106 FCMD 0x0107 Reserved for Factory Test 0x0108 Reserved for Factory Test 0x0109 Reserved for Factory Test 0x010A Reserved for Factory Test 0x010B Reserved for Factory Test 0x010C Reserved 0x010D Reserved 0x010E Reserved 0x010F Reserved Bit 7 R W R CBEIF 0 CCIF Bit 5 Bit 4 PVIOL ACCERR Bit 3 0 Bit 2 BLANK Bit 1 Bit 0 0 0 0 0 0 0 0 0
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet 2 of 4) Address Name 0x0144 TCNT (hi) 0x0145 TCNT (lo) 0x0146 TSCR1 0x0147 TTOV 0x0148 TCTL1 0x0149 Reserved 0x014A TCTL3 0x014B Reserved 0x014C TIE 0x014D TSCR2 0x014E TFLG1 0x014F TFLG2 0x0150 Reserved 0x0151 Reserved 0x0152 Reserved 0x0153 Reserved 0x0154 Reserved 0x0155 Reserved 0x0156 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet 3 of 4) Address Name 0x0157 Reserved 0x0158 TC4 (hi) 0x0159 TC4 (lo) 0x015A TC5 (hi) 0x015B TC5 (lo) 0x015C TC6 (hi) 0x015D TC6 (lo) 0x015E TC7 (hi) 0x015F TC7 (lo) 0x0160 PACTL 0x0161 PAFLG 0x0162 PACNT (hi) 0x0163 PACNT (lo) 0x0164 Reserved 0x0165 Reserved 0x0166 Reserved 0x0167 Reserved 0x0168 Reserved 0x0169 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0140 – 0x016F TIM1 (Timer 16 Bit 4 Channels) (Sheet 4 of 4) Address Name 0x016A Reserved 0x016B Reserved 0x016C Reserved 0x016D Reserved 0x016E Reserved 0x016F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0180 – 0x01AF TIM2 (Timer 16 Bit 4 Channels) (Sheet 2 of 3) Address Name 0x0189 Reserved 0x018A TCTL3 0x018B Reserved 0x018C TIE 0x018D TSCR2 0x018E TFLG1 0x018F TFLG2 0x0190 Reserved 0x0191 Reserved 0x0192 Reserved 0x0193 Reserved 0x0194 Reserved 0x0195 Reserved 0x0196 Reserved 0x0197 Reserved 0x0198 TC4 (hi) 0x0199 TC4 (lo) 0x015A TC5 (hi) 0x019B TC5 (lo) 0x019C TC6 (hi) R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0180 – 0x01AF TIM2 (Timer 16 Bit 4 Channels) (Sheet 3 of 3) Address Name 0x019D TC6 (lo) 0x019E TC7 (hi) 0x019F TC7 (lo) 0x01A0 PACTL 0x01A1 PAFLG 0x01A2 PACNT (hi) 0x01A3 PACNT (lo) 0x01A4 Reserved 0x01A5 Reserved 0x01A6 Reserved 0x01A7 Reserved 0x01A8 Reserved 0x01A9 Reserved 0x01AA Reserved 0x01AB Reserved 0x01AC Reserved 0x01AD Reserved 0x01AE Reserved 0x01AF Reserved R W R W R W R Bit 7 Bit 6 Bit 5 Bit
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x01B0 – 0x01DF Reserved Address Name 0x01B0– 0x01DF Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 CON45 CON23 CON01 PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x01E0 – 0x01FF PWM (Pulse Width Modulator) (continued) Address Name 0x01F0 PWMCNT4 0x01F1 PWMCNT5 0x01F2 PWMPER0 0x01F3 PWMPER1 0x01F4 PWMPER2 0x01F5 PWMPER3 0x01F6 PWMPER4 0x01F7 PWMPER5 0x01F8 PWMDTY0 0x01F9 PWMDTY1 0x01FA PWMDTY2 0x01FB PWMDTY3 0x01FC PWMDTY4 0x01FD PWMDTY5 0x01FE PWMSDN 0x01FF Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 1 of 4) Address Name 0x0200 PMFCFG0 0x0201 PMFCFG1 0x0202 PMFCFG2 0x0203 PMFCFG3 0x0204 PMFFCTL 0x0205 PMFFPIN 0x0206 PMFFSTA 0x0207 PMFQSMP 0x0208 PMFDMPA 0x0209 PMFDMPB 0x020A PMFDMPC 0x020B Reserved 0x020C PMFOUTC 0x020D PMFOUTB 0x020E PMFDTMS 0x020F PMFCCTL 0x0210 PMFVAL0 0x0211 PMFVAL0 0x0212 PMFVAL1 R W R W R Bit 7 Bit 6 Bit 5 Bit 4
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 2 of 4) Address Name 0x0213 PMFVAL1 0x0214 PMFVAL2 0x0215 PMFVAL2 0x0216 PMFVAL3 0x0217 PMFVAL3 0x0218 PMFVAL4 0x0219 PMFVAL4 0x021A PMFVAL5 0x021B PMFVAL5 0x021C Reserved 0x021D Reserved 0x021E Reserved 0x021F Reserved 0x0220 PMFENCA 0x0221 PMFFQCA 0x0222 PMFCNTA 0x0223 PMFCNTA 0x0224 PMFMODA 0x0225 PMFMODA R W R W R W R W R W R W R W R W R
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 3 of 4) Address Name 0x0226 PMFDTMA 0x0227 PMFDTMA 0x0228 PMFENCB 0x0229 PMFFQCB 0x022A PMFCNTB 0x022B PMFCNTB 0x022C PMFMODB 0x022D PMFMODB 0x022E PMFDTMB 0x022F PMFDTMB 0x0230 PMFENCC 0x0231 PMFFQCC 0x0232 PMFCNTC 0x0233 PMFCNTC 0x0234 PMFMODC 0x0235 PMFMODC 0x0236 PMFDTMC 0x0237 PMFDTMC 0x0238 Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0200 – 0x023F PMF (Pulse width Modulator with Fault protection) (Sheet 4 of 4) Address Name 0x0239 Reserved 0x023A Reserved 0x023B Reserved 0x023C Reserved 0x023D Reserved 0x023E Reserved 0x023F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0240 – 0x027F PIM (Port Interface Module) (Sheet 2 of 4) Address Name 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 Reserved 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP R W R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0240 – 0x027F PIM (Port Interface Module) (Sheet 3 of 4) Address Name 0x025D PPSP 0x025E Reserved 0x025F Reserved 0x0260 PTQ 0x0261 PTIQ 0x0262 DDRQ 0x0263 RDRQ 0x0264 PERQ 0x0265 PPSQ 0x0266 Reserved 0x0267 Reserved 0x0268 PTU 0x0269 PTIU 0x026A DDRU 0x026B RDRU 0x026C PERU 0x026D PPSU 0x026E MODRR 0x026F Reserved R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 0x0240 – 0x027F PIM (Port Interface Module) (Sheet 4 of 4) Address Name 0x0270 PTAD(H) 0x0271 PTAD(L) 0x0272 PTIAD(H) 0x0273 PTIAD(L) 0x0274 DDRAD(H) 0x0275 DDRAD(L) 0x0276 RDRAD(H) 0x0277 RDRAD(L) 0x0278 PERAD(H) 0x0279 PERAD(L) 0x027A PPSAD(H) 0x027B PPSAD(L) 0x027C PIEAD(H) 0x027D PIEAD(L) 0x027E PIFAD(H) 0x027F PIFAD(L) R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTAD15 PTAD14 PTAD13 PTAD12
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.2.2 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B after reset. The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID numbers. Table 1-2.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12E128 80 QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07/KWAD07 PAD06/AN06/KWAD06 PAD05/AN05/KWAD05 PAD04/AN04/KWAD04 PAD03/AN03/KWAD03 PAD02/AN02/KWAD02 PAD01/AN01/KWAD01 PAD00/AN00/KWAD00 VSS2 VDD2 PS7/SS PS6/SCK PS5/MOSI PS4/MISO PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 IOC15/PT5 IOC16/PT6 IOC17/PT7 PW10/IOC24/PU0 PW11/IOC25/PU1 XCLKS/NOACC/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PW12/IOC26/P
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MC9S12E128 64 QFN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VRH VDDA PAD06/AN06/KWAD06 PAD04/AN04/KWAD04 PAD02/AN02/KWAD02 PAD00/AN00/KWAD00 VSS2 VDD2 PS7/SS PS6/SCK PS5/MOSI PS4/MISO PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 IOC15/PT5 IOC16/PT6 IOC17/PT7 XCLKS/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST IRQ/PE1 XIRQ/PE0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PM4 PM5 SDA/PM6 SCL/PM7 FAULT0/PQ0 FAULT1/PQ1 FAULT2/PQ2 FAULT3/PQ3 VDDX VSSX
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.3.2 Signal Properties Summary Table 1-4.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-4.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.4 1.4.1 Detailed Signal Descriptions EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 1.4.2 RESET — External Reset Pin RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.4.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7 PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free cycle”. This signal will assert when the CPU is not using the bus.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.4.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. PE5 is not available in the 80-pin package version. 1.4.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register. 1.4.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) also be configured as Keypad Wake-up pins (KWU) and generate interrupts causing the MCU to exit STOP or WAIT mode. Consult the Port Integration Module (PIM) PIM_9E128 block description chapter and the ATD_10B16C block description chapter for information about pin configurations. 1.4.20 PM7 / SCL — Port M I/O Pin 7 PM7 is a general purpose input or output pin.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) PIM_9E128 block description chapter and the DAC_8B1C block description chapter for information about pin configurations. 1.4.26 PM0 / DAO2 — Port M I/O Pin 0 PM0 is a general purpose input or output pin. When the Digital to Analog module 2 (DAC2) is enabled the PM0 pin is configured as the analog output DA02 of DAC2. While in reset and immediately out of reset the PM0 pin is configured as a high impedance input pin.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.4.31 PS6 / SCK — Port S I/O Pin 6 PS6 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS6 becomes the serial clock pin, SCK. While in reset and immediately out of reset the PS6 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 block description chapter and the SPI block description chapter for information about pin configurations. 1.4.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.4.37 PS0 / RXD0 — Port S I/O Pin 0 PS0 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) receiver is enabled the PS0 pin is configured as the receive pin RXD0 of SCI0. While in reset and immediately out of reset the PS0 pin is configured as a high impedance input pin.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 block description chapter, TIM_16B4C block description chapter, and the PWM_8B6C block description chapter for information about pin configurations. 1.4.43 VDDX,VSSX — Power & Ground Pins for I/O Drivers External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. 1.4.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-5. MC9S12E128 Power and Ground Connection Summary Mnemonic Nominal Voltage VDD1, VDD2 2.5 V VSS1, VSS2 0V VDDR 3.3/5.0 V VSSR 0V VDDX 3.3/5.0 V VSSX 0V VDDA 3.3/5.0 V VSSA 0V VRH 3.3/5.0 V VRL 0V VDDPLL 2.5 V VSSPLL 0V Description Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.5 System Clock Description The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 1-10 shows the clock connections from the CRG to all modules. Consult the CRG block description chapter for details on clock generation.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.6 Modes of Operation 1.6.1 Overview Eight possible modes determine the operating configuration of the MC9S12E128. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device. 1.6.2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.7 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • Protection of the contents of FLASH, • Operation in single-chip mode, • Operation from external memory with internal FLASH disabled. The user must be reminded that part of the security must lie with the user’s code.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 1.8 Low Power Modes The microcontroller features three main low power modes. Consult the respective block description chapter for information on the module behavior in Stop, Pseudo Stop, and Wait Mode.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-9.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) Table 1-9.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.9.2.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module block description chapters for register reset states. Refer to the HCS12 MEBI block description chapter for mode dependent pin configuration of port A, B and E out of reset. Refer to the PIM block description chapter for reset configurations of all peripheral module ports.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) 1.10 Recommended Printed Circuit Board Layout The Printed Circuit Board (PCB) must be carefully laid out to ensure proper operation of the voltage regulator as well as the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1–C6). • Central point of the ground star should be the VSSR pin.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) NOTE: Oscillator in Colpitts mode. C1 VDD1 VSSA VSS1 C3 VDDA VDDX VSS2 C2 C6 VDD2 VSSX VSSR C4 C7 C8 C10 C9 R1 C11 C5 VDDR Q1 VSSPLL VDDPLL Figure 1-11. Recommended PCB Layout (112-LQFP) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) NOTE: Oscillator in Colpitts mode. VSSA C1 VDD1 C3 VSS1 VDDA VSS2 VDDX C2 C6 VDD2 VSSX VSSR C4 C7 C8 C11 C5 VDDR C10 C9 Q1 VSSPLL R1 VDDPLL Figure 1-12. Recommended PCB Layout (80-QFP) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1) NOTE: Oscillator in Colpitts mode. VSSA C1 VDD1 C3 VSS1 VDDA VSS2 C2 VDDX VDD2 C6 VSSX VSSR C4 C7 C8 C11 C5 VDDR C10 C9 Q1 VSSPLL R1 VDDPLL Figure 1-13. Recommended PCB Layout (64-QFN) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.1 Introduction The FTS128K1 module implements a 128 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 128 Kbytes organized as 1024 rows of 128 bytes with an erase sector size of eight rows (1024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.1.3 Modes of Operation See Section 2.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 2.4.1, “Flash Command Operations”. 2.1.4 Block Diagram Figure 2-1 shows a block diagram of the FTS128K1 module.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.3 Memory Map and Registers This section describes the FTS128K1 memory map and registers. 2.3.1 Module Memory Map The FTS128K1 memory map is shown in Figure 2-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes 0x5000 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x38–0x3F correspond to the PPAGE register content F
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Table 2-2. Flash Array Memory Map Summary MCU Address Range PPAGE Protectable Low Range Protectable High Range Array Relative Address1 0x0000–0x3FFF2 Unpaged (0x3D) N.A. N.A. 0x14000–0x17FFF 0x4000–0x7FFF Unpaged (0x3E) 0x4000–0x43FF N.A. 0x18000–0x1BFFF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x38 N.A. N.A. 0x00000–0x03FFF 0x39 N.A. N.A. 0x04000–0x07FFF 0x3A N.A. N.A. 0x08000–0x0BFFF 0x3B N.A. N.A.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 2-3. Detailed descriptions of each register bit are provided.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 R 6 5 4 3 2 1 0 PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 0 0 0 0 0 0 0 FDIVLD W Reset 0 = Unimplemented or Reserved Figure 2-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 2-3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Table 2-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 2-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 2-6.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 2-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Table 2-9.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPHS[1:0] FPOPEN = 1 Scenario FPLS[1:0] FPHDIS = 1 FPLDIS = 1 FPHS[1:0] FPOPEN = 0 Scenario FPLS[1:0] 0xFFFF 0xFFFF Protected Flash Figure 2-9. Flash Protection Scenarios 2.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Table 2-12. Flash Protection Scenario Transitions To Protection Scenario1 From Protection Scenario 0 1 6 X 7 1 2.3.2.6 2 X X X 3 4 X X X X 5 6 7 X X X X Allowed transitions marked with X. Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Table 2-13. FSTAT Field Descriptions Field Description 5 PVIOL Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Table 2-14. FCMD Field Descriptions Field Description 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Valid Flash commands are shown in Table 2-15. An attempt to execute any command other than those listed in Table 2-15 will set the ACCERR bit in the FSTAT register (see Section 2.3.2.6). Table 2-15. Valid Flash Command List CMDB 2.3.2.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Module Base + 0x0009 7 6 5 4 3 2 1 0 0 0 0 0 R FABLO W Reset 0 0 0 0 Figure 2-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 2.3.2.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-17. RESERVED3 All bits read 0 and are not writable. 2.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-18.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) Module Base + 0x000F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-20. RESERVED6 All bits read 0 and are not writable. 2.4 2.4.1 Functional Description Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 2-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? yes END no yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 2-21.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.3 Valid Flash Commands Table 2-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 2-16. Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 2-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Array Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 2-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 2-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 2-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.1.4 2.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.2 2.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 2.4.5). 2.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 2 128 Kbyte Flash Module (FTS128K1V1) 2.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 2-1: • FPROT — Flash Protection Register (see Section 2.3.2.5) • FSEC — Flash Security Register (see Section 2.3.2.2) 2.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.1 lntroduction The port integration module establishes the interface between the peripheral modules and the I/O pins for for ports AD, M, P, Q, S, T and U.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.1.2 Block Diagram Figure 3-1 is a block diagram of the PIM9E128V1.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.2 External Signal Description This section lists and describes the signals that connect off chip. Table 3-1 shows all the pins and their functions that are controlled by the PIM9E128V1. The order in which the pin functions are listed represents the functions priority (top – highest priority, bottom – lowest priority). Table 3-1.
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Chapter 3 Port Integration Module (PIM9E128V1) Table 3-1.
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Chapter 3 Port Integration Module (PIM9E128V1) Table 3-1.
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Chapter 3 Port Integration Module (PIM9E128V1) Table 3-1.
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Chapter 3 Port Integration Module (PIM9E128V1) Table 3-1.
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Chapter 3 Port Integration Module (PIM9E128V1) Table 3-1.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3 Memory Map and Register Definition This section provides a detailed description of all registers. Table 3-2 is a standard memory map of port integration module. Table 3-2.
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Chapter 3 Port Integration Module (PIM9E128V1) Table 3-2.
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Chapter 3 Port Integration Module (PIM9E128V1) Refer to the ATD block description chapter for information on the ATDDIEN0 and ATDDIEN1 registers. During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is disabled). 3.3.1.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.2 R Port AD Input Register (PTIAD) 7 6 5 4 3 2 1 0 PTIAD15 PTIAD14 PTIAD13 PTIAD12 PTIAD11 PTIAD10 PTIAD9 PTIAD8 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIAD0 1 1 1 1 1 1 1 1 W Reset R W Reset = Reserved or Unimplemented Figure 3-3. Port AD Input Register (PTIAD) Read: Anytime. Write: Never; writes to these registers have no effect.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.3 Port AD Data Direction Register (DDRAD) 7 6 5 4 3 2 1 0 DDRAD15 DDRAD14 DDRAD13 DDRAD12 DDRAD11 DDRAD10 DDRAD9 DDRAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 0 0 0 0 0 0 0 0 R W Reset R W Reset Figure 3-4. Port AD Data Direction Register (DDRAD) Read: Anytime. Write: Anytime. This register configures port pins PAD[15:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.4 Port AD Reduced Drive Register (RDRAD) 7 6 5 4 3 2 1 0 RDRAD15 RDRAD14 RDRAD13 RDRAD12 RDRAD11 RDRAD10 RDRAD9 RDRAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 0 0 0 0 0 0 0 0 R W Reset R W Reset Figure 3-5. Port AD Reduced Drive Register (RDRAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.5 Port AD Pull Device Enable Register (PERAD) 7 6 5 4 3 2 1 0 PERAD15 PERAD14 PERAD13 PERAD12 PERAD11 PERAD10 PERAD9 PERAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 0 0 0 0 0 0 0 0 R W Reset R W Reset Figure 3-6. Port AD Pull Device Enable Register (PERAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.6 Port AD Polarity Select Register (PPSAD) 7 6 5 4 3 2 1 0 PPSAD15 PPSAD14 PPSAD13 PPSAD12 PPSAD11 PPSAD10 PPSAD9 PPSAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 0 0 0 0 0 0 0 0 R W Reset R W Reset Figure 3-7. Port AD Polarity Select Register (PPSAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.7 Port AD Interrupt Enable Register (PIEAD) 7 6 5 4 3 2 1 0 PIEAD15 PIEAD14 PIEAD13 PIEAD12 PIEAD11 PIEAD10 PIEAD9 PIEAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PIEAD7 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 PIEAD0 0 0 0 0 0 0 0 0 R W Reset R W Reset Figure 3-8. Port AD Interrupt Enable Register (PIEAD) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.1.8 Port AD Interrupt Flag Register (PIFAD) 7 6 5 4 3 2 1 0 PIFAD15 PIFAD14 PIFAD13 PIFAD12 PIFAD11 PIFAD10 PIFAD9 PIFAD8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PIFAD7 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0 0 0 0 0 0 0 0 0 R W Reset R W Reset Figure 3-9. Port AD Interrupt Flag Register (PIFAD) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.2 Port M Port M is associated with the serial communication interface (SCI2) , Inter-IC bus (IIC) and the digital to analog converter (DAC0 and DAC1) modules. Each pin is assigned to these modules according to the following priority: IIC/SCI2/DAC1/DAC0 > general-purpose I/O. When the IIC bus is enabled, the PM[7:6] pins become SCL and SDA respectively. Refer to the IIC block description chapter for information on enabling and disabling the IIC bus.
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Chapter 3 Port Integration Module (PIM9E128V1) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. 3.3.2.3 Port M Data Direction Register (DDRM) 7 6 5 4 3 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 0 0 0 0 0 R 2 1 0 DDRM1 DDRM0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-12. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.2.4 Port M Reduced Drive Register (RDRM) 7 6 5 4 3 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 0 0 0 0 0 R 2 1 0 RDRM1 RDRM0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-13. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.2.5 Port M Pull Device Enable Register (PERM) 7 6 5 4 3 PERM7 PERM6 PERM5 PERM4 PERM3 0 0 0 0 0 R 2 1 0 PERM1 PERM0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-14. Port M Pull Device Enable Register (PERM) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.2.7 Port M Wired-OR Mode Register (WOMM) 7 6 5 4 WOMM7 WOMM6 WOMM5 WOMM4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset = Reserved or Unimplemented Figure 3-16. Port M Wired-OR Mode Register (WOMM) Read: Anytime. Write: Anytime. This register selects whether a port M output is configured as push-pull or wired-or.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.3 Port P Port P is associated with the Pulse Width Modulator (PMF) modules. Each pin is assigned according to the following priority: PMF > general-purpose I/O. When a PMF channel is enabled, the corresponding pin becomes a PWM output. Refer to the PMF block description chapter for information on enabling and disabling the PWM channels. During reset, port P pins are configured as high-impedance inputs. 3.3.3.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.3.3 R Port P Data Direction Register (DDRP) 7 6 0 0 5 4 3 2 1 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 W Reset 0 0 = Reserved or Unimplemented Figure 3-19. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures port pins PP[5:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.3.5 R Port P Pull Device Enable Register (PERP) 7 6 0 0 5 4 3 2 1 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 W Reset 0 0 = Reserved or Unimplemented Figure 3-21. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.4 Port Q Port Q is associated with the Pulse Width Modulator (PMF) modules. Each pin is assigned according to the following priority: PMF > general-purpose I/O. When a current status or fault function is enabled, the corresponding pin becomes an input. PQ[3:0] are connected to FAULT[3:0] inputs and PQ[6:4] are connected to IS[2:0] inputs of the PMF module.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.4.3 Port Q Data Direction Register (DDRQ) 7 R 6 5 4 3 2 1 0 DDRQ6 DDRQ5 DDRQ4 DDRQ3 DDRQ2 DDRQ1 DDRQ0 0 0 0 0 0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-25. Port Q Data Direction Register (DDRQ) Read: Anytime. Write: Anytime. This register configures port pins PQ[6:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.4.5 Port Q Pull Device Enable Register (PERQ) 7 R 6 5 4 3 2 1 0 PERQ6 PERQ5 PERQ4 PERQ3 PERQ2 PERQ1 PERQ0 0 0 0 0 0 0 0 0 W Reset 0 = Reserved or Unimplemented Figure 3-27. Port Q Pull Device Enable Register (PERQ) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.5 Port S Port S is associated with the serial peripheral interface (SPI) and serial communication interfaces (SCI0 and SCI1). Each pin is assigned to these modules according to the following priority: SPI/SCI1/SCI0 > general-purpose I/O. When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the SPI block description chapter for information on enabling and disabling the SPI.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.5.3 Port S Data Direction Register (DDRS) 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 3-31. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures port pins PS[7:4] and PS[2:0] as either input or output. When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data Direction Register bits have no effect.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.5.4 Port S Reduced Drive Register (RDRS) 7 6 5 4 3 2 1 0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 3-32. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Table 3-23.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.5.6 Port S Polarity Select Register (PPSS) 7 6 5 4 3 2 1 0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 R W Reset Figure 3-34. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. The Port S Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.6 Port T Port T is associated with two 4-channel timers (TIM0 and TIM1). Each pin is assigned to these modules according to the following priority: TIM1/TIM0 > general-purpose I/O. If the timer TIM0 is enabled, the channels configured for output compare are available on port T pins PT[3:0]. If the timer TIM1 is enabled, the channels configured for output compare are available on port T pins PT[7:4].
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.6.3 Port T Data Direction Register (DDRT) 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 3-38. Port T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures port pins PT[7:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.6.5 Port T Pull Device Enable Register (PERT) 7 6 5 4 3 2 1 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0 0 0 0 0 0 0 0 R W Reset Figure 3-40. Port T Pull Device Enable Register (PERT) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.7 Port U Port U is associated with one 4-channel timer (TIM2) and the pulse width modulator (PWM) module. Each pin is assigned to these modules according to the following priority: TIM2/PWM > general-purpose I/O. If the timer TIM2 is enabled, the channels configured for output compare are available on port U pins PU[3:0]. Refer to the TIM block description chapter for information on enabling and disabling the TIM module.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.7.3 Port U Data Direction Register (DDRU) 7 6 5 4 3 2 1 0 DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0 0 0 0 0 0 0 0 0 R W Reset Figure 3-44. Port U Data Direction Register (DDRU) Read: Anytime. Write: Anytime. This register configures port pins PU[7:0] as either input or output.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.7.4 Port U Reduced Drive Register (RDRU) 7 6 5 4 3 2 1 0 RDRU7 RDRU6 RDRU5 RDRU4 RDRU3 RDRU2 RDRU1 RDRU0 0 0 0 0 0 0 0 0 R W Reset Figure 3-45. Port U Reduced Drive Register (RDRU) Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Table 3-32.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.3.7.6 Port U Polarity Select Register (PPSU) 7 6 5 4 3 2 1 0 PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0 0 0 0 0 0 0 0 0 R W Reset Figure 3-47. Port U Polarity Select Register (PPSU) Read: Anytime. Write: Anytime. The Port U Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.4 Functional Description Each pin associated with ports AD, M, P, Q, S, T and U can act as general-purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor.
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Chapter 3 Port Integration Module (PIM9E128V1) PTIx 0 1 PTx PAD 0 1 DDRx 0 1 Digital Module data out output enable module enable Figure 3-49. Illustration of I/O Pin Functionality Figure 3-50 shows the state of digital inputs and outputs when an analog module drives the port. When the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read “1”.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.4.6 Polarity Select Register The Polarity Select Register selects either a pull-up or pull-down device if enabled. The pull device becomes active only if the pin is used as an input or as a wired-or output. 3.4.7 Pin Configuration Summary The following table summarizes the effect of various configuration in the Data Direction (DDR), Input/Output (I/O), reduced drive (RDR), Pull Enable (PE), Pull Select (PS) and Interrupt Enable (IE) register bits.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.5 Resets The reset values of all registers are given in the register description in Section 3.3, “Memory Map and Register Definition”. All ports start up as general-purpose inputs on reset. 3.5.1 Reset Initialization All registers including the data registers get set/reset asynchronously. Table 3-37 summarizes the port properties after reset initialization. P Table 3-37.
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Chapter 3 Port Integration Module (PIM9E128V1) 3.6 3.6.1 Interrupts General Port AD generates an edge sensitive interrupt if enabled. It offers sixteen I/O pins with edge triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector.
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Chapter 3 Port Integration Module (PIM9E128V1) tpulse Figure 3-52. Pulse Illustration A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the port integration module.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.1 Introduction This specification describes the function of the clocks and reset generator (CRGV4). 4.1.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value.
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Chapter 4 Clocks and Reset Generator (CRGV4) Voltage Regulator Power-on Reset Low Voltage Reset 1 CRG RESET CM fail Clock Monitor OSCCLK EXTAL Oscillator XTAL COP Timeout XCLKS Reset Generator Clock Quality Checker COP RTI System Reset Bus Clock Core Clock Oscillator Clock Registers XFC VDDPLL VSSPLL PLLCLK PLL Clock and Reset Control Real-Time Interrupt PLL Lock Interrupt Self-Clock Mode Interrupt 1 Refer to the device overview section for availability of the low-voltage reset feature.
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Chapter 4 Clocks and Reset Generator (CRGV4) VDDPLL CS CP MCU RS XFC Figure 4-2. PLL Loop Filter Connections 4.2.3 RESET — Reset Pin RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. 4.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the CRGV4. 4.3.
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Chapter 4 Clocks and Reset Generator (CRGV4) NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level. 4.3.2 Register Descriptions This section describes in address order all the CRGV4 registers and their individual bits.
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Chapter 4 Clocks and Reset Generator (CRGV4) Register Name ARMCOP Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = Unimplemented or Reserved Figure 4-3. CRG Register Summary (continued) 4.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.3.2.2 CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1. R 7 6 5 4 0 0 0 0 3 2 1 0 REFDV3 REFDV2 REFDV1 REFDV0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 4-5.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.3.2.4 CRG Flags Register (CRGFLG) This register provides CRG status bits and flags. 7 6 5 4 RTIF PORF LVRF LOCKIF 0 Note 1 Note 2 0 R 3 2 LOCK TRACK 1 0 SCM SCMIF W Reset 0 0 0 0 1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved Figure 4-7.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-2. CRGFLG Field Descriptions (continued) Field 1 SCMIF 0 SCM 4.3.2.5 Description Self-Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self-Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 4-17 for details on the effect of each bit. 7 6 5 4 3 2 1 0 PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI 0 0 0 0 0 0 0 0 R W Reset Figure 4-9. CRG Clock Select Register (CLKSEL) Read: anytime Write: refer to each bit for individual write conditions Table 4-4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-4. CLKSEL Field Descriptions (continued) Field Description 1 RTIWAI RTI Stops in Wait Mode Bit — Write: anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. 0 COPWAI COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP dividers whenever the part goes into wait mode. 4.3.2.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-5. PLLCTL Field Descriptions (continued) Field Description 2 PRE RTI Enable during Pseudo-Stop Bit — PRE enables the RTI during pseudo-stop mode. Write anytime. 0 RTI stops running during pseudo-stop mode. 1 RTI continues running during pseudo-stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-7.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. 7 6 WCOP RSBCK 0 0 R 5 4 3 0 0 0 2 1 0 CR2 CR1 CR0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 4-12. CRG COP Control Register (COPCTL) Read: anytime Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode Write: RSBCK: once Table 4-8.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-13.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 4-15. ARMCOP Register Diagram Read: always reads 0x0000 Write: anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
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Chapter 4 Clocks and Reset Generator (CRGV4) The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency fSCM. REFERENCE REFDV <3:0> EXTAL REDUCED CONSUMPTION OSCILLATOR OSCCLK FEEDBACK REFERENCE PROGRAMMABLE DIVIDER XTAL CRYSTAL MONITOR supplied by: LOOP PROGRAMMABLE DIVIDER LOCK LOCK DETECTOR VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO VDDPLL LOOP FILTER SYN <5:0> VDDPLL/VSSPLL XFC PIN PLLCLK VDD/VSS Figure 4-16. PLL Functional Diagram 4.4.1.
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Chapter 4 Clocks and Reset Generator (CRGV4) The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. CORE CLOCK: BUS CLOCK / ECLK Figure 4-18. Core Clock and Bus Clock Relationship 4.4.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event.
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Chapter 4 Clocks and Reset Generator (CRGV4) check window 1 VCO clock 2 50000 49999 3 1 2 3 4 5 4096 OSCCLK 4095 osc ok Figure 4-19. Check Window Example The sequence for clock quality check is shown in Figure 4-20. CM fail Clock OK POR LVR exit full stop Clock Monitor Reset Enter SCM yes check window SCM active? num=num+1 yes osc ok num=50 no num=0 no ? num<50 ? yes no SCME=1 ? no yes SCM active? yes Switch to OSCCLK no Exit SCM Figure 4-20.
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Chapter 4 Clocks and Reset Generator (CRGV4) NOTE The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo-stop mode or wait mode 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.4.6 Real-Time Interrupt (RTI) The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK (see Section Figure 4-22., “Clock Chain for RTI”). At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately.
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Chapter 4 Clocks and Reset Generator (CRGV4) running at minimum operating frequency; this mode of operation is called self-clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. See Section 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Core req’s Wait Mode. PLLWAI=1 ? no yes Clear PLLSEL, Disable PLL CWAI or SYSWAI=1 ? no yes Disable core clocks SYSWAI=1 ? no yes Disable system clocks no Enter Wait Mode CME=1 ? Wait Mode left due to external reset no yes Exit Wait w. ext.RESET CM fail ? INT ? yes no yes Exit Wait w.
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Chapter 4 Clocks and Reset Generator (CRGV4) There are five different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Self-clock mode interrupt • Real-time interrupt (RTI) If the MCU gets an external reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-11. Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 1 1 0 Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. – MCU remains in Wait Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-11. Outcome of Clock Loss in Wait Mode (continued) CME SCME SCMIE 1 1 1 CRG Actions Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. 4.4.
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Chapter 4 Clocks and Reset Generator (CRGV4) Core req’s Stop Mode. Clear PLLSEL, Disable PLL Exit Stop w. ext.RESET no Wait Mode left due to external INT ? no Enter Stop Mode PSTP=1 ? yes CME=1 ? yes no Exit Stop w. CMRESET no SCME=1 ? no yes Clock OK ? CM fail ? INT ? no yes no yes yes Exit Stop w.
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Chapter 4 Clocks and Reset Generator (CRGV4) If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and the MCU is in run mode again.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-12. Outcome of Clock Loss in Pseudo-Stop Mode CME SCME SCMIE CRG Actions 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 1 1 0 Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode. – MCU remains in Pseudo-Stop Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag.
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Chapter 4 Clocks and Reset Generator (CRGV4) Table 4-12. Outcome of Clock Loss in Pseudo-Stop Mode (continued) CME SCME SCMIE 1 1 1 CRG Actions Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. 4.4.10.
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Chapter 4 Clocks and Reset Generator (CRGV4) Definition.” All reset sources are listed in Table 4-13. Refer to the device overview chapter for related vector addresses and priorities. Table 4-13.
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Chapter 4 Clocks and Reset Generator (CRGV4) The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
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Chapter 4 Clocks and Reset Generator (CRGV4) writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector. 4.5.
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Chapter 4 Clocks and Reset Generator (CRGV4) 4.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 4-15. Refer to the device overview chapter for related vector addresses and priorities. Table 4-15. CRG Interrupt Vectors 4.6.
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Chapter 5 Oscillator (OSCV2) 5.1 Introduction The OSCV2 module provides two alternative oscillator concepts: • A low noise and low power Colpitts oscillator with amplitude limitation control (ALC) • A robust full swing Pierce oscillator with the possibility to feed in an external square wave 5.1.
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Chapter 5 Oscillator (OSCV2) 5.2 External Signal Description This section lists and describes the signals that connect off chip. 5.2.1 VDDPLL and VSSPLL — PLL Operating Voltage, PLL Ground These pins provide the operating voltage (VDDPLL) and ground (VSSPLL) for the OSCV2 circuitry. This allows the supply voltage to the OSCV2 to be independently bypassed. 5.2.
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Chapter 5 Oscillator (OSCV2) EXTAL MCU RB C3 Crystal or Ceramic Resonator RS* XTAL C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. Figure 5-2. Pierce Oscillator Connections (XCLKS = 1) EXTAL CMOS-Compatible External Oscillator (VDDPLL Level) MCU XTAL Not Connected Figure 5-3. External Clock Connections (XCLKS = 1) 5.2.
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Chapter 5 Oscillator (OSCV2) 5.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the OSCV2 module. 5.4 Functional Description The OSCV2 block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.1 Introduction The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy. 6.1.1 • • • • • • • • • • • • 6.1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Bus Clock ATD clock Clock Prescaler ATD10B16C Sequence Complete Mode and Timing Control Interrupt ATDDIEN Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 PORTAD VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL AN15 AN14 AN13 AN12 AN11 + AN10 Sample & Hold AN9 1 1 AN8 AN7 Analog MUX Comparator AN6 AN5 AN4 AN3 AN2 AN1 AN0 Figure 6-1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.2 External Signal Description This section lists all inputs to the ATD10B16C block. 6.2.1 AN15/ETRIG — Analog Input Channel 15 / External trigger Pin This pin serves as the analog input channel 15. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion. 6.2.2 ANx (x = 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins This pin serves as the analog input channel x.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) . Table 6-1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2 Register Descriptions This section describes in address order all the ATD10B16C registers and their individual bits.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Register Name 0x000D ATDDIEN1 R W 0x000E PORTAD0 R Bit 7 6 5 4 3 2 1 Bit 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W 0x000F PORTAD1 R W R BIT 9 MSB BIT 7 MSB 0x0010–0x002F W ATDDRxH– ATDDR
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Read: always read $00 in normal modes Write: unimplemented in normal modes 6.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 R 0 ASCIF W Reset 0 = Unimplemented or Reserved Figure 6-5.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-2. ATDCTL2 Field Descriptions (continued) Field Description 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 6.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 R 6 5 4 3 2 1 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 1 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 6-6.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-4. ATDCTL3 Field Descriptions (continued) Field Description 2 FIFO Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-6. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately MC9S12E128 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 0 0 0 0 0 1 0 1 R W Reset Figure 6-7.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-9. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock1 Min.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-10. ATDCTL5 Field Descriptions (continued) Field Description 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 6-13 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-13. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 MC9S12E128 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. 7 6 R 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 6-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on CC[3:0]) Table 6-14.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-14. ATDSTAT0 Field Descriptions (continued) Field Description 4 FIFOR FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.8 R Reserved Register 0 (ATDTEST0) 7 6 5 4 3 2 1 0 u u u u u u u u 1 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved u = Unaffected Figure 6-10. Reserved Register 0 (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 6.3.2.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) Table 6-16. Special Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 X X Reserved 6.3.2.10 1 0 1 0 0 VRH 1 0 1 0 1 VRL 1 0 1 1 0 (VRH+VRL) / 2 1 0 1 1 1 Reserved 1 1 X X X Reserved ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.11 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags CCF7 to CCF0 R 7 6 5 4 3 2 1 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 6-13. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 6-18.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.12 ATD Input Enable Register 0 (ATDDIEN0) 7 6 5 4 3 2 1 0 IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 0 0 0 0 0 0 0 0 R W Reset Figure 6-14. ATD Input Enable Register 0 (ATDDIEN0) Read: Anytime Write: anytime Table 6-19.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.14 Port Data Register 0 (PORTAD0) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. R 7 6 5 4 3 2 1 0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 1 1 1 1 1 1 1 1 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 W Reset Pin Function = Unimplemented or Reserved Figure 6-16.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.15 Port Data Register 1 (PORTAD1) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. R 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 1 1 1 1 1 1 1 AN 7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 W Reset Pin Function = Unimplemented or Reserved Figure 6-17.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.16 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.3.2.16.2 R (10-BIT) R (8-BIT) Right Justified Result Data 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 6-20.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.4.1.2 Analog Input Multiplexer The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. 6.4.1.3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 6.4.1.4 Analog-to-Digital (A/D) Machine The A/D machine performs analog to digital conversions.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) 6.5 Resets At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within Section 6.3, “Memory Map and Register Definition,” which details the registers and their bit fields. 6.6 Interrupts The interrupt requested by the ATD10B16C is listed in Table 6-24. Refer to MCU specification for related vector address and priority. Table 6-24.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.1 Introduction The DAC8B1C is a 8-bit, 1-channel digital-to-analog converter module. 7.1.1 Features The DAC8B1C includes these features: • 8-bit resolution. • One output independent monotonic channel. 7.1.2 Modes of Operation The DAC8B1C functions the same in normal, special, and emulation modes. It has two low-power modes, wait and stop modes. 7.1.2.1 Run Mode Normal mode of operation. 7.1.2.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) CONTROL CIRCUIT DAC CHANNEL VRL DACD DACC VREF VDDA VSSA O/P VOLTAGE DAO ANALOG SUB-BLOCK Figure 7-1. DAC8B1C Functional Block Diagram 7.2 External Signal Description The DAC8B1C module requires four external pins. These pins are listed in Table 7-1 below. Table 7-1.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.2.1 DAO — DAC Channel Output This pin is used as the analog output pin of the DAC8B1C module. The value represents the analog voltage level between VSSA and VREF. 7.2.2 VDDA — DAC Power Supply This pin serves as the power supply pin.l 7.2.3 VSSA — DAC Ground Supply This pin serves as an analog ground reference to the DAC. 7.2.4 VREF — DAC Reference Supply This pin serves as the source for the high reference potential.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.3.2 Register Descriptions This section consists of register descriptions arranged in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in descending bit order. 7.3.2.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.3.2.2 Reserved Register (DACC1) This register is reserved. Module Base + 0x0000 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-4. Reserved Register (DACC1) Read: always read $00 Write: unimplemented 7.3.2.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.3.2.4 DAC Data Register — Right Justified (DACD) Module Base + 0x0003 7 6 5 4 3 2 1 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 0 0 R W Reset Figure 7-6. DAC Data Register — Right Justified (DACD) Read: read zeroes when DJM is clear Write: unimplemented when DJM is clear The DAC data register is an 8-bit readable/writable register that stores the data to be converted when DJM bit is set.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) 7.4 Functional Description The DAC8B1C module consists of analog and digital sub-blocks. 7.4.1 Functional Description Data to be converted is written to DACD register. The data can be mapped either to left end or right end of DACD register by clearing or setting DJM bit of DACC0 register. Also, the data written to DACD can be a signed or unsigned data depending on DSGN bit of DACC0 register. See Table 7-3 below for data formats.
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Chapter 7 Digital-to-Analog Converter (DAC8B1CV1) Conversion of the data in DACD register takes place as soon as DACE bit of DACC0 is set. The transfer characteristic of the day module is shown in Figure 7-7. 256 LSB Analog Output Voltage 255 LSB 3 LSB 2 LSB $FF $FE $02 $00 $01 1 LSB Digital Input 1 LSB = 21.5 mV when VDDA = 5.5 V 1 LSB = 11.5 mV when VDDA = 3.0 V Figure 7-7. DAC8B1C Transfer Function 7.5 7.5.1 Resets General The DAC8B1C module is reset on a system reset.
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Chapter 8 Serial Communication Interface (SCIV3) 8.1 Introduction This block description chapter provides an overview of serial communication interface (SCI) module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. 8.1.
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Chapter 8 Serial Communication Interface (SCIV3) • • • • • Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection 8.1.3 Modes of Operation The SCI functions the same in normal, special, and emulation modes.
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Chapter 8 Serial Communication Interface (SCIV3) external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. 8.1.4 Block Diagram Figure 8-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
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Chapter 8 Serial Communication Interface (SCIV3) 8.2 External Signal Description The SCI module has a total of two external pins. 8.2.1 TXD — SCI Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 8.2.2 RXD — SCI Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high.
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Chapter 8 Serial Communication Interface (SCIV3) Register Name SCICR2 Bit 7 6 5 4 3 2 1 Bit 0 TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 0 0 0 BRK13 TXDIR R W SCISR1 R W SCISR2 R RAF W SCIDRH R R8 0 0 0 0 0 0 T8 W SCIDRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 = Unimplemented or Reserved Figure 8-2. SCI Registers Summary MC9S12E128 Data Sheet, Rev. 1.
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Chapter 8 Serial Communication Interface (SCIV3) 8.3.2.1 SCI Baud Rate Registers (SCIBDH and SCIBDL) 7 6 5 4 3 2 1 0 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 R W Reset Figure 8-3. SCI Baud Rate Register High (SCIBDH) Table 8-1. SCIBDH Field Descriptions Field 7 IREN 6:5 TNP[1:0] 4:0 SBR[11:8] Description Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.
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Chapter 8 Serial Communication Interface (SCIV3) NOTE If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: anytime The SCI baud rate register is used to determine the baud rate of the SCI and to control the infrared modulation/demodulation submodule. Table 8-3.
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Chapter 8 Serial Communication Interface (SCIV3) Table 8-4. SCICR1 Field Descriptions Field Description 7 LOOPS Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit.
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Chapter 8 Serial Communication Interface (SCIV3) 8.3.2.3 SCI Control Register 2 (SCICR2) 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 R W Reset Figure 8-6. SCI Control Register 2 (SCICR2) Read: anytime Write: anytime Table 8-6. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit —TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
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Chapter 8 Serial Communication Interface (SCIV3) 8.3.2.4 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provide inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.
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Chapter 8 Serial Communication Interface (SCIV3) Table 8-7. SCISR1 Field Descriptions (continued) 1 2 Field Description 3 OR Overrun Flag2 — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
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Chapter 8 Serial Communication Interface (SCIV3) 8.3.2.5 R SCI Status Register 2 (SCISR2) 7 6 5 4 3 0 0 0 0 0 2 1 BRK13 TXDIR 0 0 0 RAF W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-8. SCI Status Register 2 (SCISR2) Read: anytime Write: anytime Table 8-8. SCISR2 Field Descriptions Field Description 2 BRK13 Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long.
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Chapter 8 Serial Communication Interface (SCIV3) 8.3.2.6 SCI Data Registers (SCIDRH and SCIDRL) 7 R 6 R8 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 T8 W Reset 0 0 = Unimplemented or Reserved Figure 8-9. SCI Data Register High (SCIDRH) Table 8-9. SCIDRH Field Descriptions Field Description 7 R8 Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
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Chapter 8 Serial Communication Interface (SCIV3) 8.4 Functional Description This subsection provides a complete functional description of the SCI block, detailing the operation of the design from the end user’s perspective in a number of descriptions. Figure 8-11 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
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Chapter 8 Serial Communication Interface (SCIV3) 8.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 kbits/s and 115.2 kbits/s.
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Chapter 8 Serial Communication Interface (SCIV3) 8-BIT DATA FORMAT (BIT M IN SCICR1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 POSSIBLE PARITY BIT BIT 6 BIT 7 NEXT START BIT STOP BIT STANDARD SCI DATA INFRARED SCI DATA 9-BIT DATA FORMAT (BIT M IN SCICR1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 POSSIBLE PARITY BIT BIT 6 BIT 7 BIT 8 STOP BIT NEXT START BIT STANDARD SCI DATA INFRARED SCI DATA Figure 8-12.
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Chapter 8 Serial Communication Interface (SCIV3) 8.4.3 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR[12:0] bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter.
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Chapter 8 Serial Communication Interface (SCIV3) 8.4.4 Transmitter INTERNAL BUS ÷ 16 BAUD DIVIDER STOP SBR12–SBR0 SCI DATA REGISTERS H 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 SCTXD L PT PARITY GENERATION LOOP CONTROL BREAK (ALL 0s) PE PREAMBLE (ALL ONES) T8 SHIFT ENABLE LOAD FROM SCIDR MSB M START BUS CLOCK TO RECEIVER LOOPS RSRC TRANSMITTER CONTROL TDRE INTERRUPT REQUEST TC INTERRUPT REQUEST TDRE TE SBK TIE TC TCIE Figure 8-13. Transmitter Block Diagram 8.
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Chapter 8 Serial Communication Interface (SCIV3) flag by writing another byte to the transmitter buffer (SCIDRH/SCIDRL), while the shift register is shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is 0. Writing to the SCIBDH has no effect without also writing to SCIBDL.
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Chapter 8 Serial Communication Interface (SCIV3) If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2.
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Chapter 8 Serial Communication Interface (SCIV3) TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin 8.4.
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Chapter 8 Serial Communication Interface (SCIV3) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 8.4.5.3 Data Sampling The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Chapter 8 Serial Communication Interface (SCIV3) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 8-15 summarizes the results of the data bit samples. Table 8-15. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
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Chapter 8 Serial Communication Interface (SCIV3) In Figure 8-16 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Chapter 8 Serial Communication Interface (SCIV3) In Figure 8-18, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
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Chapter 8 Serial Communication Interface (SCIV3) Figure 8-20 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
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Chapter 8 Serial Communication Interface (SCIV3) 8.4.5.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values.
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Chapter 8 Serial Communication Interface (SCIV3) 8.4.5.5.2 Fast Data Tolerance Figure 8-23 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but continues to be sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 8-23.
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Chapter 8 Serial Communication Interface (SCIV3) 8.4.5.6.1 Idle Input Line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state.
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Chapter 8 Serial Communication Interface (SCIV3) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
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Chapter 8 Serial Communication Interface (SCIV3) chip dependent. The SCI only has a single interrupt line (SCI interrupt signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 8.5.1.1 TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register.
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Chapter 8 Serial Communication Interface (SCIV3) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 9.1.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.1.3 Block Diagram Figure 9-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. 9.2.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 9 Serial Peripheral Interface (SPIV3) Table 9-2. SPICR1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. 6 SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.3.2.2 R SPI Control Register 2 (SPICR2) 7 6 5 0 0 0 4 3 MODFEN BIDIROE 0 0 2 1 0 SPISWAI SPC0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 9-4. SPI Control Register 2 (SPICR2) Read: anytime Write: anytime; writes to the reserved bits have no effect Table 9-4. SPICR2 Field Descriptions Field Description 4 MODFEN Mode Fault Enable Bit — This bit allows the MODF failure being detected.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.3.2.3 SPI Baud Rate Register (SPIBR) 7 R 6 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 9-5. SPI Baud Rate Register (SPIBR) Read: anytime Write: anytime; writes to the reserved bits have no effect Table 9-6.
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Chapter 9 Serial Peripheral Interface (SPIV3) Table 9-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 MHz 0 0 0 0 0 1 4 6.25 MHz 0 0 0 0 1 0 8 3.125 MHz 0 0 0 0 1 1 16 1.5625 MHz 0 0 0 1 0 0 32 781.25 kHz 0 0 0 1 0 1 64 390.63 kHz 0 0 0 1 1 0 128 195.31 kHz 0 0 0 1 1 1 256 97.66 kHz 0 0 1 0 0 0 4 6.25 MHz 0 0 1 0 0 1 8 3.
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Chapter 9 Serial Peripheral Interface (SPIV3) Table 9-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.21 kHz 1 0 1 1 0 1 384 65.10 kHz 1 0 1 1 1 0 768 32.55 kHz 1 0 1 1 1 1 1536 16.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.3.2.4 R SPI Status Register (SPISR) 7 6 5 4 3 2 1 0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 9-6. SPI Status Register (SPISR) Read: anytime Write: has no effect Table 9-8. SPISR Field Descriptions Field Description 7 SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
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Chapter 9 Serial Peripheral Interface (SPIV3) The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept new data.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI Data Register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. • SCK Clock In slave mode, SCK is the SPI clock input from the master. • MISO and MOSI Pins In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. • SS Pin The SS pin is the slave select input.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device, slave devices that are not selected do not interfere with SPI bus activities.
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Chapter 9 Serial Peripheral Interface (SPIV3) Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI Data Register should now be in the slave data register and the data that was in the slave data register should be in the master.
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Chapter 9 Serial Peripheral Interface (SPIV3) In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time. 9.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system.
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Chapter 9 Serial Peripheral Interface (SPIV3) End of Idle State Begin SCK Edge Nr.
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Chapter 9 Serial Peripheral Interface (SPIV3) The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) Figure 9-11. Baud Rate Divisor Equation 9.4.5 9.4.5.
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Chapter 9 Serial Peripheral Interface (SPIV3) The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SCK and SS functions.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.4.7 Operation in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. 9.4.8 Operation in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2.
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Chapter 9 Serial Peripheral Interface (SPIV3) 9.5 Reset The reset values of registers and signals are described in the Memory Map and Registers section (see Section 9.3, “Memory Map and Register Definition”) which details the registers and their bit-fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros. 9.
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Chapter 9 Serial Peripheral Interface (SPIV3) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.1 Introduction The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 10.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 10-1. IIC Registers Start Stop Arbitration Control Clock Control In/Out Data Shift Register Interrupt bus_clock SCL SDA Address Compare Figure 10-1. IIC Block Diagram MC9S12E128 Data Sheet, Rev. 1.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.2 External Signal Description The IICV2 module has two external pins. 10.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 10.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 10.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Table 10-1.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.3.2.2 IIC Frequency Divider Register (IBFD) 7 6 5 4 3 2 1 0 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 10-3. IIC Bus Frequency Divider Register (IBFD) Read and write anytime Table 10-3. IBFD Field Descriptions Field Description 7:0 IBC[7:0] I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-5. Multiplier Factor IBC7-6 MUL 00 01 01 02 10 04 11 RESERVED The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 10-4, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 10-4.
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Chapter 10 Inter-Integrated Circuit (IICV2) The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 10-6.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-6.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-6.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-6.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-6.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-7. IBCR Field Descriptions Field Description 7 IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.
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Chapter 10 Inter-Integrated Circuit (IICV2) from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway.
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Chapter 10 Inter-Integrated Circuit (IICV2) Table 10-8. IBSR Field Descriptions (continued) Field Description 2 SRW Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.4 Functional Description This section provides a complete functional description of the IICV2. 10.4.1 I-Bus Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
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Chapter 10 Inter-Integrated Circuit (IICV2) SDA SCL START Condition STOP Condition Figure 10-9. Start and Stop Conditions 10.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master.
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Chapter 10 Inter-Integrated Circuit (IICV2) If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal. 10.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first.
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Chapter 10 Inter-Integrated Circuit (IICV2) WAIT Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure 10-10. IIC-Bus Clock Synchronization 10.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 10.4.1.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.5 Resets The reset state of each individual bit is listed in Section 10.3, “Memory Map and Register Definition,” which details the registers and their bit-fields. 10.6 Interrupts IICV2 uses only one interrupt vector. Table 10-9.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.7.1.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent.
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Chapter 10 Inter-Integrated Circuit (IICV2) 10.7.1.4 Generation of STOP A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter.
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Chapter 10 Inter-Integrated Circuit (IICV2) In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. 10.7.1.
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Chapter 10 Inter-Integrated Circuit (IICV2) Clear IBIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear IBAL Y RXAK=0 ? Last Byte To Be Read ? N N Y N Y Y IAAS=1 ? IAAS=1 ? Y N Address Transfer End Of Addr Cycle (Master Rx) ? N Y Y Y (Read) 2nd Last Byte To Be Read ? SRW=1 ? Write Next Byte To IBDR Generate Stop Signal Set TXAK =1 Generate Stop Signal Read Data From IBDR And Store ACK From Receiver ? N Read Data From IBDR And Store T
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Chapter 10 Inter-Integrated Circuit (IICV2) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.1 Introduction The Pulse width Modulator with Fault protection (PMF) module can be configured for one, two, or three complementary pairs.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.1.2 Modes of Operation Care must be exercised when using this module in the modes listed in Table 11-1. PWM outputs are placed in their inactive states in stop mode, and optionally under WAIT and freeze modes. PWM outputs will be reactivated (assuming they were active to begin with) when these modes are exited. Table 11-1. Modes When PWM Operation is Restricted 11.1.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) PRSC1 BUS CLOCK LDFQ0 MTG MULTIPLE REGISTERS OR BITS FOR TIMEBASE A, B, OR C LDFQ1 PRSC0 PRESCALER LDFQ2 LDFQ3 PMFMOD REGISTERS PMFVAL0-5 REGISTERS PWMRF PWM GENERATORS A,B,C PMFCNT REGISTERS EDGE IPOL HALF INDEP LDOK OUT0 OUT1 PWMEN OUT2 OUT3 OUT4 OUT5 OUTCTL0 OUTCTL1 OUTCTL2 OUTCTL3 OUTCTL4 DT 0—5 MUX, SWAP & CURRENT SENSE OUTCTL5 DEADTIME INSERTION PMFDTM REGISTER TOPNEG TOP/BOTTOM GENERATION BOTNEG 6
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) PWM source selection is based on a number of factors: — State of current sense pins — IPOL bit — OUTCTL bit — Center vs edge aligned SWAPA GENERATE COMPLEMENT & INSERT DEADTIME IPOLA or ISENS0 or OUTCTL0 PAD0 MSK0 OUT0 PWM GENERATOR 0 OUTCTL0 1 FAULT & POLARITY CONTROL 1 INDEPA PWM GENERATOR 1 OUT1 1 OUTCTL1 1 PAD1 MSK1 Figure 11-2. Detail of Mux, Swap, and Deadtime Functions 11.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3 11.3.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Address Name 0x0012 PMFVAL1 0x0013 PMFVAL1 0x0014 PMFVAL2 0x0015 PMFVAL2 0x0016 PMFVAL3 0x0017 PMFVAL3 0x0018 PMFVAL4 0x0019 PMFVAL4 0x001A PMFVAL5 0x001B PMFVAL5 0x001C ↓ 0X001F Reserved 0x0020 PMFENCA 0x0021 PMFFQCA 0x0022 PMFCNTA 0x0023 PMFCNTA Bit 7 6 5 4 R 3 2 0 0 1 Bit 0 LDOKA PWMRIEA PMFVAL1 W R PMFVAL1 W R PMFVAL2 W R PMFVAL2 W R PMFVAL3 W R PMFVAL3 W R PMFVAL4 W R PMFVAL4
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Address Name 0x0028 PMFENCB 0x0029 PMFFQCB 0x002A PMFCNTB 0x002B PMFCNTB 0x002C PMFMODB 0x002D PMFMODB 0x002E W 0x0030 PMFENCC 0x0031 PMFFQCC 0x0032 PMFCNTC 0x0033 PMFCNTC 0x0034 PMFMODC 0x0035 PMFMODC 0x0036 PMFDTMC 0x0037 PMFDTMC PWMENB 6 5 4 3 2 0 0 0 0 0 R LDFQB W R HALFB 0 1 Bit 0 LDOKB PWMRIEB PRSCB PWMRFB PMFCNTB W R PMFCNTB W R 0 PMFMODB W R PMFMODB W PMFDTMB R W 0x002F PMFDTMB
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2 Register Descriptions The address of a register is the sum of a base address and an address offset. The base address is defined at the chip level and the address offset is defined at the module level. 11.3.2.1 PMF Configure 0 Register (PMFCFG0) Module Base + 0x0000 7 6 5 4 3 2 1 0 WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA 0 0 0 0 0 0 0 0 R W Reset Figure 11-4.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Table 11-2. PMFCFG0 Field Descriptions (continued) Field Description 3 EDGEA Edge-Aligned or Center-Aligned PWM for Pair A — This bit determines whether PWM0 and PWM1 channels will use edge-aligned or center-aligned waveforms. It determines waveforms for Pair B and Pair C if the MTG bit is cleared. This bit cannot be modified after the WP bit is set.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.2 PMF Configure 1 Register (PMFCFG1) Module Base + 0x0001 7 R 6 5 4 3 2 1 0 BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA 0 0 0 0 0 0 0 ENHA W Reset 0 0 = Unimplemented or Reserved Figure 11-5. PMF Configure 1 Register (PMFCFG1) Read anytime. This register cannot be modified after the WP bit is set.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.3 PMF Configure 2 Register (PMFCFG2) Module Base + 0x0002 R 7 6 0 0 5 4 3 2 1 0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 11-6. PMF Configure 2 Register (PMFCFG2) Read and write anytime. Table 11-4. PMFCFG2 Field Descriptions Field 5–0 MSK[5:0] Description Mask PWMx— Where x is 0, 1, 2, 3, 4, and 5. 0 PWMx is unmasked.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.4 PMF Configure 3 Register (PMFCFG3) Module Base + 0x0003 7 6 5 PMFWAI PMFFRZ 0 0 R 4 3 2 1 0 SWAPC SWAPB SWAPA 0 0 0 0 VLMODE W Reset 0 0 0 = Unimplemented or Reserved Figure 11-7. PMF Configure 3 Register (PMFCFG3) Read and write anytime. Table 11-5.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.5 PMF Fault Control Register (PMFFCTL) Module Base + 0x0004 7 6 5 4 3 2 1 0 FMODE3 FIE3 FMODE2 FIE2 FMODE1 FIE1 FMODE0 FIE0 0 0 0 0 0 0 0 0 R W Reset Figure 11-8. PMF Fault Control Register (PMFFCTL)) Read and write anytime. Table 11-6. PMFFCTL Field Descriptions Field Description 7, 5, 3, 1 Fault x Pin Clearing Mode — This bit selects automatic or manual clearing of FAULTx pin faults.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.7 PMF Fault Status Register (PMFFSTA) Module Base + 0x0006 7 R 6 5 0 4 3 0 2 1 0 FFLAG3 0 0 FFLAG2 FFLAG1 FFLAG0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-10. PMF Fault Flag Register (PMFFSTA) Read and write anytime. Table 11-8.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Table 11-10. Qualifying Samples 1 11.3.2.9 QSMPx Number of Samples 00 1 sample1 01 5 samples 10 10 samples 11 15 samples There is an asynchronous path from fault pin to disable PWMs immediately but the fault is qualified in two bus cycles. PMF Disable Mapping Registers Module Base + 0x0008 7 6 5 4 3 2 1 0 DMP13 DMP12 DMP11 DMP10 DMP03 DMP02 DMP01 DMP00 0 0 0 0 0 0 0 0 R W Reset Figure 11-12.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) DMPx3 DMPx2 DMPx1 DMPx0 Fault0 Fault1 DISABLE PWM PIN x Fault2 Fault3 where X is 0, 1, 2, 3, 4, 5 Figure 11-15. Fault Decoder Table 11-12. Fault Mapping PWM Pin Controlling Register Bits PWM0 DMP03 – DMP00 PWM1 DMP13 – DMP10 PWM2 DMP23 – DMP20 PWM3 DMP33 – DMP30 PWM4 DMP43 – DMP40 PWM5 DMP53 – DMP50 11.3.2.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.11 PMF Output Control Bit Register (PMFOUTB) Module Base + 0x000D R 7 6 0 0 5 4 3 2 1 0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 0 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 11-17. PMF Output Control Bit Register (PMFOUTB) Read and write anytime. Table 11-14.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.12 PMF Deadtime Sample Register (PMFDTMS) Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 DT5 DT4 DT3 DT2 DT1 DT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-18. PMF Deadtime Sample Register (PMFDTMS)) Read anytime and writes have no effect. Table 11-16.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Table 11-17. PMFCCTL Field Descriptions (continued) Field Description 2 IPOLC Current Polarity — This buffered bit selects the PMF Value register for the PWM4 and PWM5 pins in top/bottom software correction in complementary mode. 0 PMF Value 4 register in next PWM cycle. 1 PMF Value 5 register in next PWM cycle. Note: The IPOLx bits take effect at the beginning of the next load cycle, regardless of the state of the load okay bit, LDOK.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.14 PMF Value 0 Register (PMFVAL0) Module Base + 0x0010 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFVAL0 W Reset 8 0 0 0 0 0 0 0 0 0 Figure 11-20. PMF Value 0 Register (PMFVAL0) Read and write anytime. Table 11-19. PMFVAL0 Field Descriptions Field Description 16–0 PMFVAL0 PMF Value 0 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM0 clock period.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.16 PMF Value 2 Register (PMFVAL2) Module Base + 0x0014 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFVAL2 W Reset 8 0 0 0 0 0 0 0 0 0 Figure 11-22. PMF Value 2 Register (PMFVAL2) Read and write anytime. Table 11-21. PMFVAL2 Field Descriptions Field Description 16–0 PMFVAL2 PMF Value 2 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM2 clock period.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.18 PMF Value 4 Register (PMFVAL4) Module Base + 0x0018 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFVAL4 W Reset 8 0 0 0 0 0 0 0 0 0 Figure 11-24. PMF Value 4 Register (PMFVAL4) Read and write anytime. Table 11-23. PMFVAL4 Field Descriptions Field Description 16–0 PMFVAL4 PMF Value 4 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM4 clock period.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.20 PMF Enable Control A Register (PMFENCA) Module Base + 0x0020 7 R 6 5 4 3 2 0 0 0 0 0 PWMENA 1 0 LDOKA PWMRIEA 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-26. PMF Enable Control A Register (PMFENCA) Read and write anytime. Table 11-25.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.21 PMF Frequency Control A Register (PMFFQCA) Module Base + 0x0021 7 6 5 4 3 2 1 0 R LDFQA HALFA PRSCA PWMRFA W Reset 0 0 0 0 0 0 0 0 Figure 11-27. PMF Frequency Control A Register (PMFFQCA) Read and write anytime. Table 11-26. PMFFQCA Field Descriptions Field Description 7–4 LDFQA Load Frequency A — This field selects the PWM load frequency according to Table 11-27. See Section 11.4.7.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Table 11-28. PWM Prescaler A PRSCA PWM Clock Frequency 00 fbus 01 fbus/2 10 fbus/4 11 fbus/8 11.3.2.22 PMF Counter A Register (PMFCNTA) Module Base + 0x0022 15 R 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFCNTA W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-28. PMF Counter A Register (PMFCNTA) Read anytime and writes have no effect. Table 11-29.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.24 PMF Deadtime A Register (PMFDTMA) Module Base + 0x0026 15 14 13 12 0 0 0 0 0 0 0 R 11 10 9 8 7 0 5 4 3 2 1 0 1 1 1 1 1 PMFDTMA W Reset 6 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 11-30. PMF Deadtime A Register (PMFDTMA) Read anytime. This register cannot be modified after the WP bit is set. Table 11-31.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.25 PMF Enable Control B Register (PMFENCB) Module Base + 0x0028 7 R 6 5 4 3 2 0 0 0 0 0 PWMENB 1 0 LDOKB PWMRIEB 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-31. PMF Enable Control B Register (PMFENCB) Read anytime and write only if MTG is set. Table 11-32.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.26 PMF Frequency Control B Register (PMFFQCB) Module Base + 0x0029 7 6 5 4 3 2 1 0 R LDFQB HALFB PRSCB PWMRFB W Reset 0 0 0 0 0 0 0 0 Figure 11-32. PMF Frequency Control B Register (PMFFQCB) Read anytime and write only if MTG is set. Table 11-33. PMFFQCB Field Descriptions Field Description 7–4 LDFQB Load Frequency B — This field selects the PWM load frequency according to Table 11-34. See Section 11.4.7.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Table 11-35. PWM Prescaler B PRSCB PWM Clock Frequency 00 fbus 01 fbus/2 10 fbus/4 11 fbus/8 11.3.2.27 PMF Counter B Register (PMFCNTB) Module Base + 0x002A 15 R 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFCNTB W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-33. PMF Counter B Register (PMFCNTB) Read anytime and writes have no effect. Table 11-36.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.29 PMF Deadtime B Register (PMFDTMB) Module Base + 0x002E 15 14 13 12 0 0 0 0 0 0 0 R 11 10 9 8 7 0 5 4 3 2 1 0 1 1 1 1 1 PMFDTMB W Reset 6 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 11-35. PMF Deadtime B Register (PMFDTMB) Read anytime and write only if MTG is set. This register cannot be modified after the WP bit is set. Table 11-38.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.30 PMF Enable Control C Register (PMFENCC) Module Base + 0x0030 7 R 6 5 4 3 2 0 0 0 0 0 PWMENC 1 0 LDOKC PWMRIEC 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-36. PMF Enable Control C Register (PMFENCC) Read anytime and write only if MTG is set. Table 11-39.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.31 PMF Frequency Control C Register (PMFFQCC) Module Base + 0x0031 7 6 5 4 3 2 1 0 R LDFQC HALFC PRSCC PWMRFC W Reset 0 0 0 0 0 0 0 0 Figure 11-37. PMF Frequency Control C Register (PMFFQCC) Read anytime and write only if MTG is set. Table 11-40. PMFFQCC Field Descriptions Field Description 7–4 LDFQC Load Frequency C — This field selects the PWM load frequency according to Table 11-41. See Section 11.4.7.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Table 11-42. PWM Prescaler C PRSCC PWM Clock Frequency 00 fbus 01 fbus/2 10 fbus/4 11 fbus/8 11.3.2.32 PMF Counter C Register (PMFCNTC) Module Base + 0x0032 15 R 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PMFCNTC W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-38. PMF Counter C Register (PMFCNTC) Read anytime and writes have no effect. Table 11-43.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.3.2.34 PMF Deadtime C Register (PMFDTMC) Module Base + 0x0000 15 14 13 12 0 0 0 0 0 0 0 R 11 10 9 8 7 0 5 4 3 2 1 0 1 1 1 1 1 PMFDTMC W Reset 6 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 11-40. PMF Deadtime C Register (PMFDTMC) Read anytime and write only if MTG is set. This register cannot be modified after the WP bit is set. Table 11-45.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4 Functional Description 11.4.1 Block Diagram A block diagram of the PMF is shown in Figure 11-1. The MTG bit allows the use of multiple PWM generators (A, B, and C) or just a single generator (A). PWM0 and PWM1 constitute Pair A, PWM2 and PWM3 constitute Pair B, and PWM4 and PWM5 constitute Pair C. 11.4.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) ALIGNMENT REFERENCE UP COUNTER MODULUS = 4 PWM OUTPUT DUTY CYCLE = 50% Figure 11-42. Edge-Aligned PWM Output NOTE Because of the equals-comparator architecture of this PMF, the modulus equals zero case is considered illegal. Therefore, the modulus register does not return to zero, and a modulus value of zero will result in waveforms inconsistent with the other modulus waveforms.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) In an edge-aligned operation, the PWM counter is an up counter. The PWM output resolution is one bus clock cycle. PWM period = PWM modulus × PWM clock period COUNT 1 2 3 4 UP COUNTER MODULUS = 4 PWM CLOCK PERIOD PWM PERIOD = 4 x PWM CLOCK PERIOD Figure 11-44. Edge-Aligned PWM Period 11.4.3.3 Duty Cycle The signed 16-bit number written to the PMF value registers is the pulse width in PWM clock periods of the PWM generator output.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Center-aligned operation is illustrated in Figure 11-45. PWM pulse width = (PWM value) × (PWM clock period) × 2 COUNT 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 UP/DOWN COUNTER MODULUS = 4 PWM VALUE = 0 0/4 = 0% PWM VALUE = 1 1/4 = 25% PWM VALUE = 2 2/4 = 50% PWM VALUE = 3 3/4 = 75% PWM VALUE = 4 4/4 = 100% Figure 11-45. Center-Aligned PWM Pulse Width Edge-aligned operation is illustrated in Figure 11-46.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.4 Independent or Complementary Channel Operation Writing a logic one to a INDEPx bit configures a pair of the PWM outputs as two independent PWM channels. Each PWM output has its own PWM value register operating independently of the other channels in independent channel operation. Writing a logic zero to a INDEPx bit configures the PWM output as a pair of complementary channels.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) In complementary channel operation, there are three additional features: • Deadtime insertion • Separate top and bottom pulse width correction for distortions are caused by deadtime inserted and the motor drive characteristics • Separate top and bottom output polarity control • Swap functionality 11.4.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) MODULUS = 4 PWM VALUE = 2 PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 1 PWM1, DEADTIME = 1 Figure 11-50. Deadtime Insertion, Center Alignment MODULUS = 3 PWM VALUE = 1 PWM Value = 3 PWM VALUE = 3 PWM VALUE = 3 PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 2 PWM1, DEADTIME = 2 Figure 11-51.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.5.1 Top/Bottom Correction In complementary mode, either the top or the bottom transistor controls the output voltage. However, deadtime has to be inserted to avoid overlap of conducting interval between the top and bottom transistor. Both transistors in complementary mode are off during deadtime, allowing the output voltage to be determined by the current status of load and introduce distortion in the output voltage.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) For a given PWM pair, whether the odd or even PMFVAL register is active depends on either: • The state of the current status pin, ISx, for that driver • The state of the odd/even correction bit, IPOLx, for that driver To correct deadtime distortion, software can decrease or increase the value in the appropriate PMFVAL register.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.5.2 Manual Correction The IPOLx bits select either the odd or the even PWM value registers to use in the next PWM cycle. Table 11-48.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) PWM0 D POSITIVE CURRENT PWM0 NEGATIVE CURRENT PWM1 Q DT0 Q DT1 CLK IS0 PIN D VOLTAGE SENSOR PWM1 CLK Figure 11-55. Current-Status Sense Scheme for Deadtime Correction If both D flip-flops latch low, DT0 = 0, DT1 = 0, during deadtime periods if current is large and flowing out of the complementary circuit. See Figure 11-55.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.5.3 Current-Sensing Correction A current sense pin, ISx, for a PWM pair selects either the odd or the even PWM value registers to use in the next PWM cycle. The selection is based on user-provided current sense circuitry driving the ISx pin high for negative current and low for positive current. Table 11-49.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) NOTE Values latched on the ISx pins are buffered so only one PWM register is used per PWM cycle. If a current status changes during a PWM period, the new value does not take effect until the next PWM period. When initially enabled by setting the PWMEN bit, no current status has previously been sampled. PWM value registers one, three, and five initially control the three PWM pairs when configured for current status correction. 11.4.5.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) UP COUNTER MODULUS = 4 UP/DOWN COUNTER MODULUS = 4 PWM = 0 PWM = 0 PWM = 1 CENTER-ALIGNED PWM = 1 POSITIVE POLARITY PWM = 2 EDGE-ALIGNED PWM = 2 POSITIVE POLARITY PWM = 3 PWM = 3 PWM = 4 PWM = 4 UP COUNTER MODULUS = 4 UP/DOWN COUNTER MODULUS = 4 PWM = 0 PWM = 0 PWM = 1 PWM = 1 EDGE-ALIGNED PWM = 2 NEGATIVE POLARITY PWM = 3 CENTER-ALIGNED PWM = 2 NEGATIVE POLARITY PWM = 3 PWM = 4 PWM = 4 Figure 11-61. PWM Polarity 11.4.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) Setting the OUTCTLx bits do not disable the PWM generators and current status sensing circuitry. They continue to run, but no longer control the output pins. When the OUTCTLx bits are cleared, the outputs of the PWM generator become the inputs to the deadtime generators at the beginning of the next PWM cycle. Software can drive the PWM outputs even when PWM enable bit (PWMEN) is set to zero.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 11-63. Clearing OUT0 with OUTCTL Set In Complementary Mode MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 11-64. Setting OUTCTL with OUT0 Set in Complementary Mode MC9S12E128 Data Sheet, Rev. 1.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.7 PWM Generator Loading 11.4.7.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.7.3 Reload Flag With a reload opportunity, regardless an actual reload occurs as determined by LDOK bit, the PWMF reload flag is set. If the PWM reload interrupt enable bit, PWMRIE is set, the PWMF flag generates CPU interrupt requests allowing software to calculate new PWM parameters in real time. When PWMRIE is not set, reloads still occur at the selected reload rate without generating CPU interrupt requests.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) HALF = 1, LDFQ[3:0] = 00 = Reload EVERY HALF-CYCLE UP/DOWN COUNTER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 0 3 2 1 1 3 2 1 0 3 2 1 1 3 3 1 1 3 1 1 1 3 1 1 0 3 3 1 PWM Figure 11-70. Half-Cycle Center-Aligned PWM Value Loading HALF = 1, LDFQ[3:0] = 00 = Reload every HALF-cycle Up/Down COUNTER LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 0 2 1 1 0 3 1 1 1 4 1 1 1 1 1 1 0 4 1 1 0 2 1 1 1 4 1 1 PWM Figure 11-71.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) LDFQ[3:0] = 00 = Reload every cycle Up-Only COUNTER LDOK = 1 MODULUS = 3 PWM VALUE = 2 PWMRF = 1 1 4 2 1 1 2 2 1 0 1 2 1 PWM Figure 11-73. Untitled Figure 11.4.7.4 Initialization Initialize all registers and set the LDOK bit before setting the PWMEN bit. With LDOK set, setting PWMEN for the first time after reset, immediately loads the PWM generator thereby setting the PWMRF flag.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) When the PWMEN bit is cleared: • The PWMx outputs will be tri-stated unless OUTCTLx = 1 • The PWM counter is cleared and does not count • The PWM generator forces its outputs to zero • The PWMRF flag and pending CPU interrupt requests are not cleared • All fault circuitry remains active unless FPINEx = 0 • Software output control remains active • Deadtime insertion continues during software output control 11.4.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.4.8.2 Automatic Fault Clearing Setting a fault mode bit, FMODEx, configures faults from the FAULTx pin for automatic clearing. When FMODEx is set, disabled PWM pins are enabled when the FAULTx pin returns to logic zero and a new PWM half cycle begins. See Figure 11-76. Clearing the FFLAGx flag does not affect disabled PWM pins when FMODEx is set. FAULT PIN PWMS ENABLED PWMS DISABLED ENABLED DISABLED PWMS ENABLED Figure 11-76.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) FAULT0 OR FAULT2 PWMS ENABLED PWMS DISABLED PWMS ENABLED FFLAGx CLEARED Figure 11-78. Manual Fault Clearing (Faults 0 & 2) - QSMP=01, 10, or 11 FAULT1 OR FAULT3 PWMS ENABLED PWMS DISABLED PWMS ENABLED FFLAGx CLEARED Figure 11-79.
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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2) 11.7 Interrupts Seven PWM sources can generate CPU interrupt requests: • Reload flag x (PWMRFx)—PWMRFx is set at the beginning of every PWM Generator x reload cycle. The reload interrupt enable bit, PWMRIEx, enables PWMRFx to generate CPU interrupt requests. where x is A, B and C. • Fault flag x (FFLAGx)—The FFLAGx bit is set when a logic one occurs on the FAULTx pin.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.1 Introduction The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B6CV1 module contains the basic features from the HC11 with some of the enhancements incorporated on the HC12, that is center aligned output mode and four available clock sources. The PWM8B6CV1 module has six channels with independent control of left and center aligned outputs on each channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.1.3 Block Diagram PWM8B6C PWM Channels Channel 5 Bus Clock Clock Select PWM Clock Period and Duty PWM5 Counter Channel 4 Period and Duty PWM4 Counter Control Channel 3 Period and Duty PWM3 Counter Channel 2 Enable Period and Duty PWM2 Counter Channel 1 Polarity Period and Duty Alignment PWM1 Counter Channel 0 Period and Duty PWM0 Counter Figure 12-1. PWM8B6CV1 Block Diagram 12.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin This pin serves as waveform output of PWM channel 2. 12.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin This pin serves as waveform output of PWM channel 1. 12.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin This pin serves as waveform output of PWM channel 0. 12.3 Memory Map and Register Definition This subsection describes in detail all the registers and register bits in the PWM8B6CV1 module.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2 Register Descriptions The following paragraphs describe in detail all the registers and register bits in the PWM8B6CV1 module.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PWMCNT3 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 PWMCNT4 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 PWMCNT5 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 PWMPER0 R W Bit 7 6 5 4 3 2 1 Bit 0 PWMPER1 R W Bit 7 6 5 4 3 2 1 Bit 0 PWMPER2 R W Bit 7 6 5 4 3 2 1 Bit 0 PWMPER3 R W Bit 7 6 5 4 3 2 1 Bit 0 PWMPER4 R W Bit 7 6 5 4 3 2 1 Bit 0 PWM
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The first PWM cycle after enabling the channel can be irregular.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-2. PWME Field Descriptions (continued) Field Description 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-3. PWMPOL Field Descriptions (continued) Field Description 2 PPOL2 Pulse Width Channel 2 Polarity 0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-4. PWMCLK Field Descriptions (continued) Field Description 2 PCLK2 Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2. 1 Clock SB is the clock source for PWM channel 2. 1 PCLK1 Pulse Width Channel 1 Clock Select 0 Clock A is the clock source for PWM channel 1. 1 Clock SA is the clock source for PWM channel 1. 0 PCLK0 Pulse Width Channel 0 Clock Select 0 Clock A is the clock source for PWM channel 0.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-6. Clock B Prescaler Selects PCKB2 PCKB1 PCKB0 Value of Clock B 0 0 0 Bus Clock 0 0 1 Bus Clock / 2 0 1 0 Bus Clock / 4 0 1 1 Bus Clock / 8 1 0 0 Bus Clock / 16 1 0 1 Bus Clock / 32 1 1 0 Bus Clock / 64 1 1 1 Bus Clock / 128 Table 12-7. Clock A Prescaler Selects 12.3.2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-8. PWMCAE Field Descriptions Field Description 5 CAE5 Center Aligned Output Mode on Channel 5 0 Channel 5 operates in left aligned output mode. 1 Channel 5 operates in center aligned output mode. 4 CAE4 Center Aligned Output Mode on Channel 4 0 Channel 4 operates in left aligned output mode. 1 Channel 4 operates in center aligned output mode. 3 CAE3 Center Aligned Output Mode on Channel 3 1 Channel 3 operates in left aligned output mode.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) NOTE Change these bits only when both corresponding channels are disabled. Table 12-9. PWMCTL Field Descriptions Field Description 6 CON45 Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high-order byte and channel 5 becomes the low-order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP).
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-9. Reserved Register (PWMTST) Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. 12.3.2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2.9 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2.11 Reserved Registers (PWMSCNTx) The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-13. Reserved Register (PWMSCNTA) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-14.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register – 1.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12-18. PWM Channel Counter Registers (PWMCNT3) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12-19.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: • Left aligned output (CAEx = 0) • PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1) • PWMx period = channel clock period * (2 * PWMPERx) For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 12-26. PWM Channel Period Registers (PWMPER5) Read: anytime Write: anytime 12.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-27. PWM Channel Duty Registers (PWMDTY0) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-28. PWM Channel Duty Registers (PWMDTY1) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 R W Reset Figure 12-29.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. 7 6 5 PWMIF PWMIE R 0 W Reset 4 3 2 0 PWM5IN PWMLVL 1 0 PWM5INL PWM5ENA 0 0 PWMRSTRT 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-33. PWM Shutdown Register (PWMSDN) Read: anytime Write: anytime Table 12-10.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.4 Functional Description 12.4.1 PWM Clock Select There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Clock A M U X Clock to PWM Ch 0 Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 PCLK0 8-Bit Down Counter Count = 1 M U X Load PWMSCLA Clock SA DIV 2 PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 8 16 32 64 128 M U X Clock B 4 M U X Clock to PWM Ch 4 Clock B/2, B/4, B/6,....
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.4.1.2 Clock Scale The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are available for clock SB.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.4.1.3 Clock Select Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. 12.4.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.4.2.1 PWM Enable Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 12.4.2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.4.2.4 PWM Timer Counters Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference Figure 12-34 for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 12-35. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) 12.4.2.5 Left Aligned Outputs The PWM timer provides the choice of two types of outputs, left aligned or center aligned outputs. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Shown below is the output waveform generated. E = 100 ns DUTY CYCLE = 75% PERIOD = 400 ns Figure 12-37. PWM Left Aligned Output Example Waveform 12.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to 0x0000.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 12-40. PWM 16-Bit Mode When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel clock select control bits.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Table 12-12 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 12-12. 16-bit Concatenation Mode Summary 12.4.2.
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Chapter 12 Pulse-Width Modulator (PWM8B6CV1) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 13 Timer Module (TIM16B4CV1) 13.1 Introduction The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer contains 4 complete input capture/output compare channels IOC[7:4] and one pulse accumulator.
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Chapter 13 Timer Module (TIM16B4CV1) 13.1.3 Block Diagrams Bus clock Prescaler 16-bit Counter Timer overflow interrupt Timer channel 4 interrupt Registers Channel 4 Input capture Output compare Channel 5 Input capture Output compare Timer channel 7 interrupt PA overflow interrupt PA input interrupt Channel 6 Input capture Output compare 16-bit Pulse accumulator Channel 7 Input capture Output compare IOC4 IOC5 IOC6 IOC7 Figure 13-1. TIM16B4CV1 Block Diagram MC9S12E128 Data Sheet, Rev. 1.
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Chapter 13 Timer Module (TIM16B4CV1) TIMCLK (Timer clock) CLK1 CLK0 Intermodule Bus Clock select (PAMOD) Edge detector PT7 PACLK PACLK / 256 PACLK / 65536 Prescaled clock (PCLK) 4:1 MUX Interrupt PACNT MUX Divide by 64 M clock Figure 13-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer PTn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 13-3. Interrupt Flag Setting MC9S12E128 Data Sheet, Rev. 1.
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Chapter 13 Timer Module (TIM16B4CV1) PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OM7 OL7 OC7M7 Figure 13-4. Channel 7 Output Compare/Pulse Accumulator Logic NOTE For more information see the respective functional descriptions in Section 13.4, “Functional Description,” of this document. 13.2 External Signal Description The TIM16B4CV1 module has a total of four external pins. 13.2.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 13.3.1 Module Memory Map The memory map for the TIM16B4CV1 module is given below in Table 13-1. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B4CV1 module and the address offset for each register. Table 13-1.
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Chapter 13 Timer Module (TIM16B4CV1) 2 Only writable in special modes (test_mode = 1). Write has no effect; return 0 on read 4 Write to these registers have no meaning or effect during input capture. 3 13.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 13 Timer Module (TIM16B4CV1) Register Name 0x000B Reserved R W 0x000D TSCR2 W R R R W 0x000F TFLG2 W 0x0010–0x0017 Reserved W R R R 0x0018–0x001F TCxH–TCxL W R W 0x0020 PACTL 0x0021 PAFLG 0x0022 PACNTH 0x0023 PACNTL 0x0024–0x002F Reserved 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.1 Timer Input Capture/Output Compare Select (TIOS) 7 6 5 4 IOS7 IOS6 IOS5 IOS4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset Figure 13-6. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime Table 13-2. TIOS Field Descriptions Field 7:4 IOS[7:4] 13.3.2.2 Description Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.3 Output Compare 7 Mask Register (OC7M) 7 6 5 4 OC7M7 OC7M6 OC7M5 OC7M4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset Figure 13-8. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime Table 13-4.
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Chapter 13 Timer Module (TIM16B4CV1) 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 R W Reset Figure 13-11. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word.
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Chapter 13 Timer Module (TIM16B4CV1) Table 13-6. TSCR1 Field Descriptions (continued) Field Description 5 TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally.
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Chapter 13 Timer Module (TIM16B4CV1) Table 13-8. TCTL1/TCTL2 Field Descriptions Field Description 7:4 OMx Output Mode — These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.9 Timer Control Register 3 (TCTL3) 7 6 5 4 3 2 1 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 R W Reset Figure 13-15. Timer Control Register 3 (TCTL3) Read: Anytime Write: Anytime. Table 13-10. TCTL3/TCTL4 Field Descriptions Field 7:0 EDGnB EDGnA Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits. Table 13-11.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.10 Timer Interrupt Enable Register (TIE) 7 6 5 4 C7I C6I C5I C4I 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset Figure 13-16. Timer Interrupt Enable Register (TIE) Read: Anytime Write: Anytime. Table 13-12. TIE Field Descriptions Field Description 7:4 C7I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register.
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Chapter 13 Timer Module (TIM16B4CV1) Table 13-14. Timer Clock Selection PR2 PR1 PR0 Timer Clock 0 0 0 Bus Clock / 1 0 0 1 Bus Clock / 2 0 1 0 Bus Clock / 4 0 1 1 Bus Clock / 8 1 0 0 Bus Clock / 16 1 0 1 Bus Clock / 32 1 1 0 Bus Clock / 64 1 1 1 Bus Clock / 128 NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 13.3.2.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) 7 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOF W Reset 0 Unimplemented or Reserved Figure 13-19. Main Timer Interrupt Flag 2 (TFLG2) TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
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Chapter 13 Timer Module (TIM16B4CV1) Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 13.3.2.
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Chapter 13 Timer Module (TIM16B4CV1) Table 13-17. PACTL Field Descriptions (continued) Field 1 PAOVI 0 PAI Description Pulse Accumulator Overflow Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. Table 13-18. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.16 Pulse Accumulator Flag Register (PAFLG) R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 PAOVF PAIF 0 0 W Reset 0 0 0 0 0 0 Unimplemented or Reserved Figure 13-23. Pulse Accumulator Flag Register (PAFLG) Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register. Table 13-20.
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Chapter 13 Timer Module (TIM16B4CV1) 13.3.2.17 Pulse Accumulators Count Registers (PACNT) 15 14 13 12 11 10 9 0 PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 0 0 0 0 0 0 0 0 R W Reset Figure 13-24. Pulse Accumulator Count Register High (PACNTH) 7 6 5 4 3 2 1 0 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 0 0 0 0 0 0 0 0 R W Reset Figure 13-25.
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Chapter 13 Timer Module (TIM16B4CV1) 13.4 Functional Description This section provides a complete functional description of the timer TIM16B4CV1 block. Please refer to the detailed timer block diagram in Figure 13-26 as necessary.
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Chapter 13 Timer Module (TIM16B4CV1) 13.4.1 Prescaler The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). 13.4.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs.
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Chapter 13 Timer Module (TIM16B4CV1) The minimum pulse width for the PAI input is greater than two bus clocks. 13.4.5 Event Counter Mode Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count. NOTE The PACNT input and timer channel 7 use the same pin IOC7.
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Chapter 13 Timer Module (TIM16B4CV1) 13.6 Interrupts This section describes interrupts originated by the TIM16B4CV1 block. Table 13-21 lists the interrupts generated by the TIM16B4CV1 to communicate with the MCU. Table 13-21.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.1 Introduction The VREG3V3V2 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical). 14.1.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.1.3 Block Diagram Figure 14-1 shows the function principle of VREG3V3V2 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages. VDDPLL REG2 VDDR REG VSSPLL VDDA VDD REG1 LVD LVR LVR POR POR VSS VSSA VREGEN CTRL LVI REG: Regulator Core LVD: Low Voltage Detect CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset PIN Figure 14-1.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.2 External Signal Description Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 14-1 shows all signals of VREG3V3V2 associated with pins. Table 14-1.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.2.3 VDD, VSS — Regulator Output1 (Core Logic) Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In shutdown mode an external supply at VDD/VSS can replace the voltage regulator. 14.2.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.3.2 Register Descriptions The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual bits. 14.3.2.1 VREG3V3V2 — Control Register (VREGCTRL) The VREGCTRL register allows to separately enable features of VREG3V3V2. R 7 6 5 4 3 2 0 0 0 0 0 LVDS 1 0 LVIE LVIF 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-2. VREG3V3 — Control Register (VREGCTRL) Table 14-3.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) The regulator is a linear series regulator with a bandgap reference in its full-performance mode and a voltage clamp in reduced-power mode. All load currents flow from input VDDR to VSS or VSSPLL, the reference circuits are connected to VDDA and VSSA. 14.4.2 Full-Performance Mode In full-performance mode, a fraction of the output voltage (VDD) and the bandgap reference voltage are fed to an operational amplifier.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) 14.5 Resets This subsection describes how VREG3V3V2 controls the reset of the MCU.The reset values of registers and signals are provided in Section 14.3, “Memory Map and Register Definition”. Possible reset sources are listed in Table 14-4. Table 14-4. VREG3V3V2 — Reset Sources Reset Source 14.5.
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Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 15 Background Debug Module (BDMV4) 15.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in Figure 15-1. HOST SYSTEM BKGD 16-BIT SHIFT REGISTER ADDRESS ENTAG BDMACT INSTRUCTION DECODE AND EXECUTION TRACE SDV ENBDM BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS STANDARD BDM FIRMWARE LOOKUP TABLE CLKSW Figure 15-1.
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Chapter 15 Background Debug Module (BDMV4) • • • • • • • Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from the standard BDM firmware lookup table Instruction tagging capability Software control of BDM operation during wait mode Software selectable clocks When secured, hardware commands are allowed to access the register space in special single-chip mode, if the FLASH and EEPROM erase tests fail.
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Chapter 15 Background Debug Module (BDMV4) • • • • • BKGD — Background interface pin TAGHI — High byte instruction tagging pin TAGLO — Low byte instruction tagging pin BKGD and TAGHI share the same pin. TAGLO and LSTRB share the same pin. NOTE Generally these pins are shared as described, but it is best to check the device overview chapter to make certain. All MCUs at the time of this writing have followed this pin sharing scheme. 15.2.
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Chapter 15 Background Debug Module (BDMV4) 15.3 Memory Map and Register Definition A summary of the registers associated with the BDM is shown in Figure 15-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow. 15.3.1 Module Memory Map Table 15-1.
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Chapter 15 Background Debug Module (BDMV4) 15.3.
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Chapter 15 Background Debug Module (BDMV4) 15.3.2.1 BDM Status Register (BDMSTS) 7 6 R 5 BDMACT ENBDM 4 3 SDV TRACE ENTAG 2 1 0 UNSEC 0 02 0 0 0 0 0 0 0 CLKSW W Reset: Special single-chip mode: Special peripheral mode: All other modes: 11 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 0 0 0 0 = Implemented (do not alter) Figure 15-3.
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Chapter 15 Background Debug Module (BDMV4) Table 15-2. BDMSTS Field Descriptions (continued) Field Description 5 ENTAG Tagging Enable — This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active.
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Chapter 15 Background Debug Module (BDMV4) Table 15-3. BDM Clock Sources PLLSEL CLKSW BDMCLK 1 0 Alternate clock (refer to the device overview chapter to determine the alternate clock source) 1 1 Bus clock dependent on the PLL MC9S12E128 Data Sheet, Rev. 1.
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Chapter 15 Background Debug Module (BDMV4) 15.3.2.2 BDM CCR Holding Register (BDMCCR) 7 6 5 4 3 2 1 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 0 R W Reset Figure 15-4. BDM CCR Holding Register (BDMCCR) Read: All modes Write: All modes NOTE When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR register.
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Chapter 15 Background Debug Module (BDMV4) 15.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 15.4.3, “BDM Hardware Commands.” Target system memory includes all memory that is accessible by the CPU.
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Chapter 15 Background Debug Module (BDMV4) sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed.
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Chapter 15 Background Debug Module (BDMV4) The BDM hardware commands are listed in Table 15-5. Table 15-5. Hardware Commands Opcode (hex) Data Description BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable handshake. This command does not issue an ACK pulse.
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Chapter 15 Background Debug Module (BDMV4) firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 15-6. Table 15-6. Firmware Commands Command1 Opcode (hex) Data Description READ_NEXT 62 16-bit data out Increment X by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator.
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Chapter 15 Background Debug Module (BDMV4) NOTE 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out.
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Chapter 15 Background Debug Module (BDMV4) HARDWARE READ 8 BITS AT ∼16 TC/BIT 16 BITS AT ∼16 TC/BIT COMMAND ADDRESS 150-BC DELAY 16 BITS AT ∼16 TC/BIT DATA NEXT COMMAND 150-BC DELAY HARDWARE WRITE COMMAND ADDRESS DATA NEXT COMMAND 44-BC DELAY FIRMWARE READ COMMAND NEXT COMMAND DATA 32-BC DELAY FIRMWARE WRITE COMMAND DATA NEXT COMMAND 64-BC DELAY GO, TRACE COMMAND NEXT COMMAND BC = BUS CLOCK CYCLES TC = TARGET CLOCK CYCLES Figure 15-6. BDM Command Structure 15.4.
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Chapter 15 Background Debug Module (BDMV4) clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 15-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time.
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Chapter 15 Background Debug Module (BDMV4) CLOCK TARGET SYSTEM HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 15-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 15-9 shows the host receiving a logic 0 from the target.
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Chapter 15 Background Debug Module (BDMV4) 15.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU.
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Chapter 15 Background Debug Module (BDMV4) Figure 15-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation.
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Chapter 15 Background Debug Module (BDMV4) 15.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse.
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Chapter 15 Background Debug Module (BDMV4) READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST (OUT OF SCALE) BKGD PIN READ_BYTE SYNC RESPONSE FROM THE TARGET (OUT OF SCALE) MEMORY ADDRESS HOST READ_STATUS TARGET HOST TARGET BDM DECODE AND STARTS TO EXECUTES THE READ_BYTE CMD NEW BDM COMMAND HOST TARGET NEW BDM COMMAND Figure 15-12. ACK Abort Procedure at the Command Level Figure 15-13 shows a conflict between the ACK pulse and the SYNC request pulse.
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Chapter 15 Background Debug Module (BDMV4) The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. • ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol.
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Chapter 15 Background Debug Module (BDMV4) 15.4.9 SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1.
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Chapter 15 Background Debug Module (BDMV4) If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. 15.4.11 Instruction Tagging The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer.
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Chapter 15 Background Debug Module (BDMV4) If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDC is running in a frequency much greater than the CPU frequency.
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Chapter 15 Background Debug Module (BDMV4) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 16 Debug Module (DBGV1) 16.1 Introduction This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform. The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP mode) and furthermore provides an on-chip trace buffer with flexible triggering capability (DBG mode). The DBG module provides for non-intrusive debug of application software. The DBG module is optimized for the HCS12 16-bit architecture. 16.1.
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Chapter 16 Debug Module (DBGV1) The DBG in DBG mode includes these distinctive features: • Three comparators (A, B, and C) — Dual mode, comparators A and B used to compare addresses — Full mode, comparator A compares address and comparator B compares data — Can be used as trigger and/or breakpoint — Comparator C used in LOOP1 capture mode or as additional breakpoint • Four capture modes — Normal mode, change-of-flow information is captured based on trigger specification — Loop1 mode, comparator C is dynami
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Chapter 16 Debug Module (DBGV1) — — — — 16.1.2 Data associated with event B trigger modes Detail report mode stores address and data for all cycles except program (P) and free (f) cycles Current instruction address when in profiling mode BGND is not considered a change-of-flow (cof) by the debugger Modes of Operation There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive of the other and selected via a software programmable control bit.
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Chapter 16 Debug Module (DBGV1) CLOCKS AND CONTROL SIGNALS BKP CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS ...... RESULTS SIGNALS CONTROL SIGNALS READ/WRITE CONTROL CONTROL BITS ......
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Chapter 16 Debug Module (DBGV1) DBG READ DATA BUS ADDRESS BUS ADDRESS/DATA/CONTROL REGISTERS CONTROL WRITE DATA BUS READ DATA BUS READ/WRITE TRACER BUFFER CONTROL LOGIC MATCH_A COMPARATOR A MATCH_B COMPARATOR B DBG MODE ENABLE CONTROL MATCH_C LOOP1 COMPARATOR C TAG FORCE CHANGE-OF-FLOW INDICATORS MCU IN BDM DETAIL EVENT ONLY STORE CPU PROGRAM COUNTER POINTER INSTRUCTION LAST CYCLE M U X REGISTER BUS CLOCK WRITE DATA BUS M U X READ DATA BUS M U X LAST INSTRUCTION ADDRESS PROFILE CAPTUR
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Chapter 16 Debug Module (DBGV1) 16.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in Figure 16-3. Detailed descriptions of the registers and bits are given in the subsections that follow. 16.3.1 Module Memory Map Table 16-2. DBGV1 Memory Map Address Offset 16.3.
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Chapter 16 Debug Module (DBGV1) Name1 DBGTBH DBGTBL DBGCNT DBGCCX(2) DBGCCH(2) DBGCCL(2) DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H R 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBF 0 W R CNT W R W R W R W R W R W R W R W R W DBGCBX BKP1X W DBGCBL BKP1L 6 W DBGCAL BKP0L DBGCBH BKP1H Bit 7 R R W R W PAGSEL EXTCMP Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 B
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Chapter 16 Debug Module (DBGV1) 16.3.2.1 Debug Control Register 1 (DBGC1) NOTE All bits are used in DBG mode only. 7 6 5 4 3 DBGEN ARM TRGSEL BEGIN DBGBRK 0 0 0 0 0 R 2 1 0 0 CAPMOD W Reset 0 0 0 = Unimplemented or Reserved Figure 16-4. Debug Control Register (DBGC1) NOTE This register cannot be written if BKP mode is enabled (BKABEN in DBGC2 is set). Table 16-3.
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Chapter 16 Debug Module (DBGV1) Table 16-3. DBGC1 Field Descriptions (continued) Field Description 3 DBGBRK DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based on comparator A and B to the CPU upon completion of a tracing session. Please refer to Section 16.4.3, “Breakpoints,” for further details. 0 CPU break request not enabled 1 CPU break request enabled 1:0 CAPMOD Capture Mode Field — See Table 16-4 for capture mode field definitions.
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Chapter 16 Debug Module (DBGV1) 16.3.2.2 R Debug Status and Control Register (DBGSC) 7 6 5 4 AF BF CF 0 3 2 1 0 0 0 TRG W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-5. Debug Status and Control Register (DBGSC) Table 16-5. DBGSC Field Descriptions Field Description 7 AF Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
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Chapter 16 Debug Module (DBGV1) 16.3.2.3 R Debug Trace Buffer Register (DBGTB) 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 u u u u u u u u W Reset = Unimplemented or Reserved Figure 16-6. Debug Trace Buffer Register High (DBGTBH) R 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 u u u u u u u u W Reset = Unimplemented or Reserved Figure 16-7. Debug Trace Buffer Register Low (DBGTBL) Table 16-7.
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Chapter 16 Debug Module (DBGV1) 16.3.2.4 R Debug Count Register (DBGCNT) 7 6 TBF 0 0 0 5 4 3 2 1 0 0 0 0 CNT W Reset 0 0 0 = Unimplemented or Reserved Figure 16-8. Debug Count Register (DBGCNT) Table 16-8. DBGCNT Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0].
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Chapter 16 Debug Module (DBGV1) 16.3.2.5 Debug Comparator C Extended Register (DBGCCX) 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 16-9. Debug Comparator C Extended Register (DBGCCX) Table 16-10. DBGCCX Field Descriptions Field Description 7:6 PAGSEL Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 16-11. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e.
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Chapter 16 Debug Module (DBGV1) DBGCXX 7 DBGCXH[15:12] EXTCMP 6 BIT 15 BIT 14 XAB16 XAB15 XAB14 PIX2 PIX1 PIX0 0 5 0 4 3 2 1 BIT 0 XAB21 XAB20 XAB19 XAB18 XAB17 PIX7 PIX6 PIX5 PIX4 PIX3 BIT 13 BIT 12 BKP/DBG MODE PAGSEL SEE NOTE 1 PORTK/XAB PPAGE SEE NOTE 2 NOTES: 1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 16-11. 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00. Figure 16-10.
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Chapter 16 Debug Module (DBGV1) Table 16-13. Comparator C Compares PAGSEL EXTCMP Compare High-Byte Compare x0 No compare DBGCCH[7:0] = AB[15:8] x1 EXTCMP[5:0] = XAB[21:16] DBGCCH[7:0] = XAB[15:14],AB[13:8] 16.3.2.7 R Debug Control Register 2 (DBGC2) 7 6 5 4 3 2 1 0 BKABEN1 FULL BDM TAGAB BKCEN2 TAGC2 RWCEN2 RWC2 0 0 0 0 0 0 0 0 W Reset 1 When BKABEN is set (BKP mode), all bits in DBGC2 are available.
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Chapter 16 Debug Module (DBGV1) Table 16-14. DBGC2 Field Descriptions (continued) Field Description 1 RWCEN Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled for comparator C. RWCEN is not useful for tagged breakpoints. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison 0 RWC 16.3.2.8 R Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for comparator C.
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Chapter 16 Debug Module (DBGV1) Table 16-15. DBGC3 Field Descriptions (continued) Field Description 5:4 Breakpoint Mask High Byte and Low Byte of Data (Second Address) — In dual mode, these bits may be BKBMB[H:L] used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in Table 16-17. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare.
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Chapter 16 Debug Module (DBGV1) Table 16-17. Breakpoint Mask Bits for Second Address (Dual Mode) BKBMBH:BKBMBL DBGCBH DBGCBL Full address compare Yes 1 Yes Yes 0:1 256 byte address range Yes1 Yes No 1:1 16K byte address range Yes1 No No x:0 1 Address Compare DBGCBX If PPAGE is selected. Table 16-18.
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Chapter 16 Debug Module (DBGV1) 16.3.2.9 Debug Comparator A Extended Register (DBGCAX) 7 6 5 4 3 2 1 0 0 0 0 R PAGSEL EXTCMP W Reset 0 0 0 0 0 Figure 16-15. Debug Comparator A Extended Register (DBGCAX) Table 16-19. DBGCAX Field Descriptions Field 7:6 PAGSEL Description Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 16-20. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e.
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Chapter 16 Debug Module (DBGV1) 16.3.2.10 Debug Comparator A Register (DBGCA) 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 16-17. Debug Comparator A Register High (DBGCAH) 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 16-18. Debug Comparator A Register Low (DBGCAL) Table 16-21.
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Chapter 16 Debug Module (DBGV1) 16.3.2.12 Debug Comparator B Register (DBGCB) 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 16-20. Debug Comparator B Register High (DBGCBH) 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 16-21. Debug Comparator B Register Low (DBGCBL) Table 16-23.
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Chapter 16 Debug Module (DBGV1) The breakpoint can operate in dual address mode or full breakpoint mode. Each of these modes is discussed in the subsections below. 16.4.1.1 Dual Address Mode When dual address mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter background debug mode or to initiate a software interrupt based upon the state of BDM in DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests.
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Chapter 16 Debug Module (DBGV1) NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
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Chapter 16 Debug Module (DBGV1) control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to match the upper addresses as shown in Table 16-11. NOTE If a tagged-type C breakpoint is set at the same address as an A/B tagged-type trigger (including the initial entry in an inside or outside range trigger), the C breakpoint will have priority and the trigger will not be recognized. 16.4.2.1.
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Chapter 16 Debug Module (DBGV1) 16.4.2.3 Begin- and End-Trigger The definitions of begin- and end-trigger as used in the DBG module are as follows: • Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are filled. • End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected. 16.4.2.
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Chapter 16 Debug Module (DBGV1) least six addresses higher than address A (or B is lower than A) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 16.4.2.5.4 Event-Only B (Store Data) In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in DBGC1 is ignored.
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Chapter 16 Debug Module (DBGV1) 16.4.2.5.8 Inside Range (A ≤ address ≤ B) In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries.
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Chapter 16 Debug Module (DBGV1) 16.4.2.6 Capture Modes The DBG in DBG mode can operate in four capture modes. These modes are described in the following subsections. 16.4.2.6.1 Normal Mode In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow information or data will be stored depending on TRG in DBGSC. 16.4.2.6.
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Chapter 16 Debug Module (DBGV1) 16.4.2.6.3 Detail Mode In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where his code was in error. 16.4.2.6.
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Chapter 16 Debug Module (DBGV1) the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace buffer. 16.4.2.9 Reading Data from Trace Buffer The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid words can be determined.
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Chapter 16 Debug Module (DBGV1) Table 16-26.
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Chapter 16 Debug Module (DBGV1) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 17 Interrupt (INTV1) 17.1 Introduction This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in Figure 17-1.
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Chapter 17 Interrupt (INTV1) The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug mode request, and three system reset vector requests. All interrupt related exception requests are managed by the interrupt sub-block (INT). 17.1.
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Chapter 17 Interrupt (INTV1) 17.2 External Signal Description Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data. 17.3 Memory Map and Register Definition Detailed descriptions of the registers and associated bits are given in the subsections that follow. 17.3.1 Module Memory Map Table 17-1. INT Memory Map Address Offset 17.3.
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Chapter 17 Interrupt (INTV1) Table 17-2. ITCR Field Descriptions Field Description 4 WRTINT Write to the Interrupt Test Registers Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs. 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead.
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Chapter 17 Interrupt (INTV1) 17.3.2.3 Highest Priority I Interrupt (Optional) 7 6 5 4 3 2 1 PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 1 1 1 1 0 0 1 R 0 0 W Reset 0 = Unimplemented or Reserved Figure 17-4. Highest Priority I Interrupt Register (HPRIO) Read: Anytime Write: Only if I mask in CCR = 1 Table 17-4.
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Chapter 17 Interrupt (INTV1) 17.5 Resets The INT supports three system reset exception request types: normal system reset or power-on-reset request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request must be decoded by the system and the proper request made to the core. The INT will then provide the service routine address for the type of reset requested. 17.
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Chapter 17 Interrupt (INTV1) 17.7 Exception Priority The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 17-5. Table 17-5.
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Chapter 17 Interrupt (INTV1) MC9S12E128 Data Sheet, Rev. 1.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.1 Introduction This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory map controller (MMC) sub-blocks. Figure 18-1 is a block diagram of the MEBI. In Figure 18-1, the signals on the right hand side represent pins that are accessible externally. On some chips, these may not all be bonded out.
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Internal Bus Addr[19:0] EXT BUS I/F CTL Data[15:0] ADDR DATA Port K ADDR PK[7:0]/ECS/XCS/X[19:14] Port A REGS PA[7:0]/A[15:8]/ D[15:8]/D[7:0] Port B Chapter 18 Multiplexed External Bus Interface (MEBIV3) PB[7:0]/A[7:0]/ D[7:0] (Control) ADDR DATA CPU pipe info PIPE CTL IRQ interrupt XIRQ interrupt IRQ CTL TAG CTL BDM tag info mode Port E ECLK CTL PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ BKGD BKGD/MODC/TAGHI Control signal(s) Data signal (
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.1.2 • • • • • • • • Modes of Operation Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.2 External Signal Description In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins. Some pins may not be bonded out in all implementations.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-1. External System Pins Associated With MEBI (continued) Pin Name PE5/IPIPE0/MODA PE4/ECLK PE3/LSTRB/ TAGLO PE2/R/W PE1/IRQ PE0/XIRQ PK7/ECS PK6/XCS PK5/X19 thru PK0/X14 Pin Functions Description MODA At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode. PE5 General-purpose I/O pin, see PORTE and DDRE registers. IPIPE0 Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3 Memory Map and Register Definition A summary of the registers associated with the MEBI sub-block is shown in Table 18-2. Detailed descriptions of the registers and bits are given in the subsections that follow. On most chips the registers are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions. 18.3.1 Module Memory Map Table 18-2.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2 18.3.2.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.2 Port B Data Register (PORTB) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 AB/DB7 AB/DB6 AB/DB5 AB/DB4 AB/DB3 AB/DB2 AB/DB1 AB/DB0 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 R W Reset Single Chip Expanded Wide, Emulation Narrow with IVIS, and Peripheral Expanded Narrow Figure 18-3.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.3 Data Direction Register A (DDRA) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 18-4. Data Direction Register A (DDRA) Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port A. When port A is operating as a general-purpose I/O port, DDRA determines the primary direction for each port A pin.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.4 Data Direction Register B (DDRB) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 18-5. Data Direction Register B (DDRB) Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port B. When port B is operating as a general-purpose I/O port, DDRB determines the primary direction for each port B pin.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.5 R Reserved Registers 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-6. Reserved Register R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-7. Reserved Register R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-8.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.6 Port E Data Register (PORTE) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 Bit 1 Bit 0 0 0 0 0 0 0 u u NOACC MODB or IPIPE1 or CLKTO MODA or IPIPE0 ECLK LSTRB or TAGLO R/W IRQ XIRQ R W Reset Alternate Pin Function = Unimplemented or Reserved u = Unaffected by reset Figure 18-10.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.7 Data Direction Register E (DDRE) 7 6 5 4 3 2 Bit 7 6 5 4 3 Bit 2 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-11. Data Direction Register E (DDRE) Read: Anytime when register is in the map Write: Anytime when register is in the map Data direction register E is associated with port E.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-6. PEAR Field Descriptions Field Description 7 NOACCE CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle. This bit has no effect in single-chip or special peripheral modes.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-7. MODE Field Descriptions Field Description 7:5 MOD[C:A] Mode Select Bits — These bits indicate the current operating mode. If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then MODC, MODB, and MODA are writable with the exception that you cannot change to or from special peripheral mode If MODC = 1, MODB = 0, and MODA = 0, then MODC is write never.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-8.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE These bits have no effect when the associated pin(s) are outputs. (The pull resistors are inactive.) Table 18-9. PUCR Field Descriptions Field Description 7 PUPKE Pull resistors Port K Enable 0 Port K pull resistors are disabled. 1 Enable pull resistors for port K input pins.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) Table 18-10. RDRIV Field Descriptions Field Description 7 RDRK Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. 4 RDPE Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. 1 RDPB Reduced Drive of Port B 0 All port B output pins have full drive enabled.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.13 Reserved Register R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 18-17. Reserved Register This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to this register have no effect. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.15 Port K Data Register (PORTK) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 ECS XCS XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 R W Reset Alternate Pin Function Figure 18-19. Port K Data Register (PORTK) Read: Anytime Write: Anytime This port is associated with the internal memory expansion emulation pins.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.3.2.16 Port K Data Direction Register (DDRK) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 18-20. Port K Data Direction Register (DDRK) Read: Anytime Write: Anytime This register determines the primary direction for each port K pin configured as general-purpose I/O. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set.
PAGE 536
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.4 18.4.1 Functional Description Detecting Access Type from External Signals The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle.
PAGE 537
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.4.3 Modes of Operation The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 18-16). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. Table 18-16.
PAGE 538
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.4.3.1 Normal Operating Modes These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. 18.4.3.1.1 Normal Single-Chip Mode There is no external expansion bus in this mode.
PAGE 539
Chapter 18 Multiplexed External Bus Interface (MEBIV3) The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 18.4.3.1.
PAGE 540
Chapter 18 Multiplexed External Bus Interface (MEBIV3) 18.4.3.1.5 Emulation Expanded Narrow Mode Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B.
PAGE 541
Chapter 18 Multiplexed External Bus Interface (MEBIV3) control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 18.4.3.2.
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Chapter 18 Multiplexed External Bus Interface (MEBIV3) NOTE When the system is operating in a secure mode, internal visibility is not available (i.e., IVIS = 1 has no effect). Also, the IPIPE signals will not be visible, regardless of operating mode. IPIPE1–IPIPE0 will display 0es if they are enabled. In addition, the MOD bits in the MODE control register cannot be written. 18.4.5 Low-Power Options The MEBI does not contain any user-controlled options for reducing power consumption.
PAGE 543
Chapter 19 Module Mapping Control (MMCV4) 19.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in Figure 19-1.
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Chapter 19 Module Mapping Control (MMCV4) 19.1.
PAGE 545
Chapter 19 Module Mapping Control (MMCV4) Table 19-1. MMC Memory Map (continued) Address Offset Register Reserved Access — . . . . — Memory Size Register 0 (MEMSIZ0) R Memory Size Register 1 (MEMSIZ1) R . . . . Program Page Index Register (PPAGE) Reserved R/W — MC9S12E128 Data Sheet, Rev. 1.
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Chapter 19 Module Mapping Control (MMCV4) 19.3.
PAGE 547
Chapter 19 Module Mapping Control (MMCV4) Write: Once in normal and emulation modes, anytime in special modes NOTE Writes to this register take one cycle to go into effect. This register initializes the position of the internal RAM within the on-chip system memory map. Table 19-2. INITRM Field Descriptions Field Description 7:3 Internal RAM Map Position — These bits determine the upper five bits of the base address for the system’s RAM[15:11] internal RAM array.
PAGE 548
Chapter 19 Module Mapping Control (MMCV4) 19.3.2.2 Initialization of Internal Registers Position Register (INITRG) 7 R 6 5 4 3 REG14 REG13 REG12 REG11 0 0 0 0 0 2 1 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 19-4. Initialization of Internal Registers Position Register (INITRG) Read: Anytime Write: Once in normal and emulation modes and anytime in special modes This register initializes the position of the internal registers within the on-chip system memory map.
PAGE 549
Chapter 19 Module Mapping Control (MMCV4) 19.3.2.3 Initialization of Internal EEPROM Position Register (INITEE) 7 6 5 4 3 EE15 EE14 EE13 EE12 EE11 — — — — — R 2 1 0 0 0 EEON W Reset1 — — — 1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved Figure 19-5.
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Chapter 19 Module Mapping Control (MMCV4) 19.3.2.4 Miscellaneous System Control Register (MISC) R 7 6 5 4 0 0 0 0 3 2 1 0 EXSTR1 EXSTR0 ROMHM ROMON W Reset: Expanded or Emulation 0 0 0 0 1 1 0 —1 Reset: Peripheral or Single Chip 0 0 0 0 1 1 0 1 Reset: Special Test 0 0 0 0 1 1 0 0 1. The reset state of this bit is determined at the chip integration level. = Unimplemented or Reserved Figure 19-6.
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Chapter 19 Module Mapping Control (MMCV4) 19.3.2.5 R Reserved Test Register 0 (MTST0) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-7. Reserved Test Register 0 (MTST0) Read: Anytime Write: No effect — this register location is used for internal test purposes. 19.3.2.6 R Reserved Test Register 1 (MTST1) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 W Reset = Unimplemented or Reserved Figure 19-8.
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Chapter 19 Module Mapping Control (MMCV4) 19.3.2.7 Memory Size Register 0 (MEMSIZ0) 7 R REG_SW0 6 5 4 3 2 1 0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0 — — — — — — — W Reset — = Unimplemented or Reserved Figure 19-9. Memory Size Register 0 (MEMSIZ0) Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section.
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Chapter 19 Module Mapping Control (MMCV4) Table 19-9. Allocated RAM Memory Space (continued) 1 2 ram_sw2:ram_sw0 Allocated RAM Space RAM Mappable Region INITRM Bits Used RAM Reset Base Address1 101 12K bytes 16K bytes 2 RAM[15:14] 0x1000 110 14K bytes 2 RAM[15:14] 0x0800 111 16K bytes RAM[15:14] 0x0000 16K bytes 16K bytes The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009.
PAGE 554
Chapter 19 Module Mapping Control (MMCV4) Table 19-11. Allocated FLASH/ROM Physical Memory Space Allocated FLASH or ROM Space rom_sw1:rom_sw0 00 0K byte 01 16K bytes 10 48K bytes(1) 11 64K bytes(1) NOTES: 1. The ROMHM software bit in the MISC register determines the accessibility of the FLASH/ROM memory space. Please refer to Section 19.3.2.8, “Memory Size Register 1 (MEMSIZ1),” for a detailed functional description of the ROMHM bit. Table 19-12.
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Chapter 19 Module Mapping Control (MMCV4) The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF as defined in Table 19-14. CALL and RTC instructions have special access to read and write this register without using the address bus.
PAGE 556
Chapter 19 Module Mapping Control (MMCV4) of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages all CPU read data bus swapping operations. 19.4.2 Address Decoding As data flows on the core address bus, the MMC decodes the address information, determines whether the internal core register or firmware space, the peripheral space or a memory register or array space is being addressed and generates the correct select signal.
PAGE 557
Chapter 19 Module Mapping Control (MMCV4) In emulation modes, if the EMK bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port K are removed from the on-chip memory map and become external accesses. 19.4.2.2 Emulation Chip Select Signal When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 7 is used as an active-low emulation chip select signal, ECS.
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Chapter 19 Module Mapping Control (MMCV4) Table 19-17.
PAGE 559
Chapter 19 Module Mapping Control (MMCV4) • • • Calculates the address of the next instruction after the CALL instruction (the return address), and pushes this 16-bit value onto the stack. Pushes the old PPAGE value onto the stack. Calculates the effective address of the subroutine, refills the queue, and begins execution at the new address on the selected page of the expansion window. This sequence is uninterruptable; there is no need to inhibit interrupts during CALL execution.
PAGE 560
Chapter 19 Module Mapping Control (MMCV4) Table 19-21 summarize the functionality of these signals based upon the allocated memory configuration. Again, this signal information is only available externally when the EMK bit is set and the system is in an expanded mode. Table 19-18.
PAGE 561
Chapter 19 Module Mapping Control (MMCV4) A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in Figure 19-12. 0x0000 61 16K FLASH (UNPAGED) 0x4000 62 16K FLASH (UNPAGED) ONE 16K FLASH/ROM PAGE ACCESSIBLE AT A TIME (SELECTED BY PPAGE = 0 TO 63) 0x8000 0 1 2 3 59 60 61 62 63 16K FLASH (PAGED) 0xC000 63 These 16K FLASH/ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register.
PAGE 562
Chapter 19 Module Mapping Control (MMCV4) MC9S12E128 Data Sheet, Rev. 1.
PAGE 563
Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. The part is specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the part is not tested in production test in the intermediate range.
PAGE 564
Appendix A Electrical Characteristics VDD1, VSS1, VDD2 and VSS2 are the supply pins for the internal logic. VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted.
PAGE 565
Appendix A Electrical Characteristics injection current may flow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only.
PAGE 566
Appendix A Electrical Characteristics A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification.
PAGE 567
Appendix A Electrical Characteristics A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4.
PAGE 568
Appendix A Electrical Characteristics Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P P = I INT IO = DD ⋅V DD +I DDPLL ⋅V DDPLL +I DDA ⋅V DDA ∑i RDSON ⋅ IIOi2 Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.
PAGE 569
Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable, e.g., not all pins feature pull up/down resistances. Table A-6. 5V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Symbol Min Typ Max Unit Input High Voltage VIH 0.65*VDD5 — — V T Input High Voltage VIH — — VDD5 + 0.3 V P Input Low Voltage VIL — — 0.
PAGE 570
Appendix A Electrical Characteristics Table A-7. Preliminary 3.3V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Symbol Min Typ Max Unit Input High Voltage VIH 0.65*VDD5 — — V T Input High Voltage VIH — — VDD5 + 0.3 V P Input Low Voltage VIL — — 0.35*VDD5 V T Input Low Voltage VIL VSS5 – 0.
PAGE 571
Appendix A Electrical Characteristics A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals.
PAGE 572
Appendix A Electrical Characteristics A.2 Voltage Regulator This section describes the characteristics of the on chip voltage regulator. Table A-9. Voltage Regulator Electrical Parameters Num C 1 P Input Voltages 3 P 4 5 6 7 P P P C Characteristic Symbol Min Typical Max Unit VVDDR,A 2.97 — 5.5 V Output Voltage Core Full Performance Mode VDD 2.35 2.5 2.75 V Output Voltage PLL Full Performance Mode VDDPLL 2.35 2.5 2.
PAGE 573
Appendix A Electrical Characteristics A.2.1 Chip Power-up and LVI/LVR Graphical Explanation Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1. V VDDA VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR Figure A-1. Voltage Regulator — Chip Power-up and Voltage Drops (not scaled) A.2.2 A.2.2.
PAGE 574
Appendix A Electrical Characteristics A.3 A.3.1 Startup, Oscillator and PLL Startup Table A-11 summarizes several startup characteristics explained in this section. Table A-11. Startup Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 T POR release level VPORR 2 T POR assert level VPORA 0.
PAGE 575
Appendix A Electrical Characteristics A.3.1.4 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. A.3.1.5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. A.3.1.
PAGE 576
Appendix A Electrical Characteristics A.3.2 Oscillator The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail.
PAGE 577
Appendix A Electrical Characteristics A.3.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.3.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL Cs fosc 1 refdv+1 fref ∆ fcmp R Phase XFC Pin VCO KΦ KV fvco Detector Loop Divider 1 synr+1 1 2 Figure A-2.
PAGE 578
Appendix A Electrical Characteristics The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response. 2 ⋅ ζ ⋅ f ref f ref 1 f C < ------------------------------------------ ------ → f C < ------------- ;( ζ = 0.
PAGE 579
Appendix A Electrical Characteristics 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-3. Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
PAGE 580
Appendix A Electrical Characteristics Table A-13. PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 P 2 Rating Symbol Min Self Clock Mode frequency fSCM D VCO locking range 3 D Lock Detector transition from Acquisition to Tracking mode 4 D Lock Detection 5 D 6 Max Unit 1 5.5 MHz fVCO 8 50 MHz |∆trk| 3 4 %1 |∆Lock| 0 1.5 %1 Un-Lock Detection |∆unl| 0.5 2.
PAGE 581
Appendix A Electrical Characteristics A.4 A.4.1 Flash NVM NVM Timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum.
PAGE 582
Appendix A Electrical Characteristics A.4.1.4 Mass Erase Erasing a NVM block takes: t mass 1 ≈ 20000 ⋅ ------------------------f NVMOP The setup times can be ignored for this operation. A.4.1.5 Blank Check The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ≈ location ⋅ t cyc + 10 ⋅ t cyc Table A-14.
PAGE 583
Appendix A Electrical Characteristics A.4.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table A-15.
PAGE 584
Appendix A Electrical Characteristics Typical Endurance 500 Typical Endurance [103 Cycles] 450 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 140 Operating Temperature TJ [°C] ------ Flash MC9S12E128 Data Sheet, Rev. 1.
PAGE 585
Appendix A Electrical Characteristics A.5 SPI Characteristics This section provides electrical parametrics and ratings for the SPI. In Table A-16 the measurement conditions are listed. Table A-16. Measurement Conditions Description Value Drive mode full drive mode — 50 pF (20% / 80%) VDDX V Load capacitance CLOAD, on all outputs Thresholds for delay measurement points A.5.1 Unit Master Mode In Figure A-4 the timing diagram for master mode with transmission format CPHA=0 is depicted.
PAGE 586
Appendix A Electrical Characteristics In Figure A-5 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS1 (OUTPUT) 1 2 12 13 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 11 9 MOSI (OUTPUT) PORT DATA LSB IN MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-5.
PAGE 587
Appendix A Electrical Characteristics A.5.2 Slave Mode In Figure A-6 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. SS (INPUT) 1 12 13 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 10 8 7 9 MISO (OUTPUT) see note SLAVE MSB 5 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 MOSI (INPUT) BIT 6 . . . 1 MSB IN LSB IN NOTE: Not defined! Figure A-6.
PAGE 588
Appendix A Electrical Characteristics In Table A-18 the timing characteristics for slave mode are listed. Table A-18.
PAGE 589
Appendix A Electrical Characteristics A.6 ATD Characteristics This section describes the characteristics of the analog to digital converter. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test. A.6.1 ATD Operating Characteristics — 5V Range The Table A-19 shows conditions under which the ATD operates.
PAGE 590
Appendix A Electrical Characteristics A.6.2 ATD Operating Characteristics — 3.3V Range The Table A-20 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-20. 3.
PAGE 591
Appendix A Electrical Characteristics A.6.3.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN). A.6.3.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted.
PAGE 592
Appendix A Electrical Characteristics A.6.4 ATD Accuracy — 5V Range Table A-22 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-22. 5V ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.
PAGE 593
Appendix A Electrical Characteristics For the following definitions see also Figure A-8. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = --------------------------- – 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = n 0 -–n ∑ DNL(i) = -------------------1LSB V –V i=1 MC9S12E128 Data Sheet, Rev. 1.
PAGE 594
Appendix A Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi 0x3FF 8-Bit Absolute Error Boundary 0x3FE 0x3FD 0x3FC 0xFF 0x3FB 0x3FA 0x3F9 0x3F8 0xFE 0x3F7 0x3F6 0x3F5 0xFD 10-Bit Resolution 0x3F3 9 Ideal Transfer Curve 8 2 8-Bit Resolution 0x3F4 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 50 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-8.
PAGE 595
Appendix A Electrical Characteristics A.7 DAC Characteristics This section describes the characteristics of the digital to analog converter. A.7.1 DAC Operating Characteristics Table A-24. DAC Electrical Characteristics (Operating) Num C Characteristic 1 D DAC Supply 2 D DAC Supply Current Condition D 3 D Reference Potential D 4 D Reference Supply Current 5 D Input Current, Channel Off1 6 D Operating Temperature Range Symbol Min Typ Max Unit VDDA 3.135 — 5.
PAGE 596
Appendix A Electrical Characteristics 1, 2 3 4 ECLK PE4 5 9 Addr/Data (read) PA, PB 6 16 15 10 data addr data 7 8 12 Addr/Data (write) PA, PB data 14 13 data addr 17 11 19 18 Non-Multiplexed Addresses PK5:0 20 21 22 23 ECS PK7 24 25 26 27 28 29 30 31 32 33 34 R/W PE2 LSTRB PE3 NOACC PE7 35 36 IPIPO0 IPIPO1, PE6,5 Figure A-9. General External Bus Timing MC9S12E128 Data Sheet, Rev. 1.
PAGE 597
Appendix A Electrical Characteristics Table A-26. Expanded Bus Timing Characteristics (5V Range) Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF 1 Num C Rating 1 P Frequency of operation (E-clock) 2 P Cycle time 3 D Pulse width, E low high1 Symbol Min Typ Max Unit fo 0 — 25.
PAGE 598
Appendix A Electrical Characteristics Table A-27. Expanded Bus Timing Characteristics (3.3V Range) Conditions are VDDX=3.3V+/-10%, Junction Temperature -40˚C to +140˚C, CLOAD = 50pF 1 Num C Rating 1 P Frequency of operation (E-clock) 2 P Cycle time 3 D Pulse width, E low high1 Symbol Min Typ Max Unit fo 0 — 16.0 MHz tcyc 62.
PAGE 599
Appendix B Package Information Appendix B Package Information B.1 64-Pin QFN Package Figure B-1. 64-Pin QFN Mechanical Dimensions (Case no. TBD) MC9S12E128 Data Sheet, Rev. 1.
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Appendix B Package Information B.2 80-Pin QFP Package L 41 60 61 B D D S V B P B 0.20 M C A-B L 0.20 M H A-B -B- 0.05 D -A- S S S 40 -A-,-B-,-DDETAIL A DETAIL A 21 80 1 A 0.20 M H A-B S F 20 -DD S 0.05 A-B J S 0.20 M C A-B S D N S E M D DETAIL C 0.20 M C A-B C -CSEATING PLANE DATUM PLANE -H- 0.10 H S D S SECTION B-B VIEW ROTATED 90 ° M G U T DATUM -HPLANE R K W X Q DIM A B C D E F G H J K L M N P Q R S T U V W X NOTES: 1.
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Appendix B Package Information B.3 112-Pin LQFP Package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 C L 84 VIEW Y 108X G X X=L, M OR N VIEW Y V B L M B1 28 57 29 F D 56 0.13 N S1 A S C2 VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE θ3 T θ R R2 R 0.25 R1 GAGE PLANE (K) C1 M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 C AA J V1 E θ1 (Y) (Z) VIEW AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.
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Appendix C Ordering Information Appendix C Ordering Information MC9S12 E128 C FU Package Option Temperature Option Device Title Controller Family Package Options FC = 64QFN FU = 80QFP PV = 112LQFP Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Figure C-1. Order Part Number Coding Table C-1 lists the part number coding based on the package and temperature. Table C-1. Part Number Coding Part Number Temp.
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Appendix C Ordering Information Table C-2 summarizes the package option and size configuration. Table C-2. Package Option Summary Part Number MC9S12E128 MC9S12E64 MC9S12E32 1 Package Temp.
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Appendix C Ordering Information MC9S12E128 Data Sheet, Rev. 1.
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