Datasheet

Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
MC9S12E128 Data Sheet, Rev. 1.07
118 Freescale Semiconductor
2.4.4 Flash Reset Sequence
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash array memory according to Table 2-1:
• FPROT — Flash Protection Register (see Section 2.3.2.5)
• FSEC — Flash Security Register (see Section 2.3.2.2)
2.4.4.1 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/array being erased is not guaranteed.
2.4.5 Interrupts
The Flash module can generate an interrupt when all Flash commands have completed execution or the
Flash address, data, and command buffers are empty.
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
2.4.5.1 Description of Interrupt Operation
Figure 2-26 shows the logic used for generating interrupts.
The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to
discriminate for the generation of interrupts.
Figure 2-26. Flash Interrupt Implementation
For a detailed description of these register bits, refer to Section 2.3.2.4, “Flash Configuration Register
(FCNFG)” and Section 2.3.2.6, “Flash Status Register (FSTAT)”.
Table 2-17. Flash Interrupt Sources
Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask
Flash Address, Data, and Command
Buffers are empty
CBEIF
(FSTAT register)
CBEIE I Bit
All Flash commands have completed
execution
CCIF
(FSTAT register)
CCIE I Bit
CBEIF
CBEIE
CCIF
CCIE
FLASH INTERRUPT REQUEST