Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
120 Freescale Semiconductor
3.1.2 Block Diagram
Figure 3-1 is a block diagram of the PIM9E128V1.
Figure 3-1. PIM9E128V1 Block Diagram
Port T
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
TIM0/TIM1
IOC04
IOC05
IOC06
IOC07
IOC14
IOC15
IOC16
IOC17
Port P
PP0
PP1
PP2
PP3
PP4
PP5
Port S
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
RXD
TXD
RXD
TXD
SDI/MISO
SDO/MOSI
SCK
SS
SCI0
SCI1
SPI
Port Q
Port M
SCI2
RXD2
TXD2
IIC
SDA
SCL
Port B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port E
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Port K
PK0
PK1
PK2
PK3
PK7
PK4
PK5
ADDR8/DATA8
ADDR9/DATA9
ADDR10/DATA10
ADDR11/DATA11
ADDR12/DATA12
ADDR13/DATA13
ADDR14/DATA14
ADDR15/DATA15
ADDR0/DATA0
ADDR1/DATA1
ADDR2/DATA2
ADDR3/DATA3
ADDR4/DATA4
ADDR5/DATA5
ADDR6/DATA6
ADDR7/DATA7
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
IPIPE0/MODA
NOACC/XCLKS
IPIPE1/MODB
XADDR15
XADDR16
XADDR17
ECS/ROMONE
XADRR18
XADDR19
CORE
XADDR14
CAN0 routing
BKGD/MODC/TAGHI
BKGD
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FAULT0
FAULT1
FAULT2
FAULT3
IS0
PMF
PM7
DAO1
DAO0
PM6
PM5
PM4
PM3
PM1
PM0
Port U
IOC24
IOC25
IOC27
Port Integration Module
TIM2
PU0
PU1
PU2
PU3
PU4
PU5
PU6
PU7
ADC
PAD8
PAD9
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
Port AD
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
Interrupt Logic
PQ6
PQ5
PQ4
PQ3
PQ2
PQ1
PQ0
IOC26
PW15
PW14
PW13
PW12
PW11
PW04
PW03
PW02
PW01
PW00
PW10
PW05
MUX
PWM
PK6
XCS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
DAC1
DAC0
IS2
IS1
KWAD0
KWAD1
KWAD2
KWAD3
KWAD4
KWAD5
KWAD6
KWAD7
KWAD8
KWAD9
KWAD10
KWAD11
KWAD12
KWAD13
KWAD14
KWAD15