Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 131
3.3.1.3 Port AD Data Direction Register (DDRAD)
Read: Anytime. Write: Anytime.
This register configures port pins PAD[15:0] as either input or output.
If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated
ATDDIEN0(1) bit. If the associated ATDDIEN0(1) bit is set to 1 (digital input buffer is enabled), a read
on PTADx returns the value on port AD pin. If the associated ATDDIEN0(1) bit is set to 0 (digital input
buffer is disabled), a read on PTADx returns a 1.
76543210
R
DDRAD15 DDRAD14 DDRAD13 DDRAD12 DDRAD11 DDRAD10 DDRAD9 DDRAD8
W
Reset 0 0 0 00000
76543210
R
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
W
Reset 0 0 0 00000
Figure 3-4. Port AD Data Direction Register (DDRAD)
Table 3-3. DDRAD Field Descriptions
Field Description
15:0
DDRAD[15:0]
Data Direction Port AD
0 Associated pin is configured as input.
1 Associated pin is configured as output.