Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
136 Freescale Semiconductor
3.3.1.8 Port AD Interrupt Flag Register (PIFAD)
Read: Anytime. Write: Anytime.
Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling
based on the state of the corresponding PPSADx bit. To clear each flag, write “1” to the corresponding
PIFADx bit. Writing a “0” has no effect.
NOTE
If the ATDDIEN0(1) bit of the associated pin is set to 0 (digital input buffer
is disabled), active edges can not be detected.
76543210
R
PIFAD15 PIFAD14 PIFAD13 PIFAD12 PIFAD11 PIFAD10 PIFAD9 PIFAD8
W
Reset 0 0 0 00000
76543210
R
PIFAD7 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0
W
Reset 0 0 0 00000
Figure 3-9. Port AD Interrupt Flag Register (PIFAD)
Table 3-8. PIFAD Field Descriptions
Field Description
15:0
PIFAD[15:0]
Interrupt Flags Port AD
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.