Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
142 Freescale Semiconductor
3.3.3 Port P
Port P is associated with the Pulse Width Modulator (PMF) modules. Each pin is assigned according to
the following priority: PMF > general-purpose I/O.
When a PMF channel is enabled, the corresponding pin becomes a PWM output. Refer to the PMF block
description chapter for information on enabling and disabling the PWM channels.
During reset, port P pins are configured as high-impedance inputs.
3.3.3.1 Port P I/O Register (PTP)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRPx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRPx) is set to 0 (input), a read returns the value of the pin.
The PMF function takes precedence over the general-purpose I/O function if the associated PWM channel
is enabled. The PWM channels 5-0 are outputs if the respective channels are enabled.
3.3.3.2 Port P Input Register (PTIP)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
76543210
R0 0
PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
PMF:
PW05 PW04 PW03 PW02 PW01 PW00
Reset 0 0 0 00000
= Reserved or Unimplemented
Figure 3-17. Port P I/O Register (PTP)
76543210
R 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
Reset 0 0 u uuuuu
= Reserved or Unimplemented u = Unaffected by reset
Figure 3-18. Port P Input Register (PTIP)