Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 145
3.3.4 Port Q
Port Q is associated with the Pulse Width Modulator (PMF) modules. Each pin is assigned according to
the following priority: PMF > general-purpose I/O.
When a current status or fault function is enabled, the corresponding pin becomes an input. PQ[3:0] are
connected to FAULT[3:0] inputs and PQ[6:4] are connected to
IS[2:0] inputs of the PMF module. Refer
to the PMF block description chapter for information on enabling and disabling these PMF functions.
During reset, port Q pins are configured as high-impedance inputs.
3.3.4.1 Port Q I/O Register (PTQ)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRQx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRQx) is set to 0 (input), a read returns the value of the pin.
3.3.4.2 Port Q Input Register (PTIQ)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
76543210
R0
PTQ5 PTQ5 PTQ4 PTQ3 PTQ2 PTQ1 PTQ0
W
PMF:
IS2 IS1 IS0 FAULT3 FAULT2 FAULT1 FAULT0
Reset 0 0 0 00000
= Reserved or Unimplemented
Figure 3-23. Port Q I/O Register (PTQ)
76543210
R 0 PTIQ6 PTIQ5 PTIQ4 PTIQ3 PTIQ2 PTIQ1 PTIQ0
W
Reset 0 u u uuuuu
= Reserved or Unimplemented u = Unaffected by reset
Figure 3-24. Port Q Input Register (PTIQ)