Datasheet
Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
146 Freescale Semiconductor
3.3.4.3 Port Q Data Direction Register (DDRQ)
Read: Anytime. Write: Anytime.
This register configures port pins PQ[6:0] as either input or output.
If a PMF function is enabled, the corresponding pin is forced to be an input and the associated Data
Direction Register bit has no effect. If a PMF channel is disabled, the corresponding Data Direction
Register bit reverts to control the I/O direction of the associated pin.
3.3.4.4 Port Q Reduced Drive Register (RDRQ)
Read:Anytime. Write:Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
76543210
R0
DDRQ6 DDRQ5 DDRQ4 DDRQ3 DDRQ2 DDRQ1 DDRQ0
W
Reset 0 0 0 00000
= Reserved or Unimplemented
Figure 3-25. Port Q Data Direction Register (DDRQ)
Table 3-18. DDRQ Field Descriptions
Field Description
6:0
DDRQ[6:0]
Data Direction Port Q
0 Associated pin is configured as input.
1 Associated pin is configured as output.
76543210
R0
RDRQ6 RDRQ5 RDRQ4 RDRQ3 RDRQ2 RDRQ1 RDRQ0
W
Reset 0 0 0 00000
= Reserved or Unimplemented
Figure 3-26. Port Q Reduced Drive Register (RDRQ)
Table 3-19. RDRQ Field Descriptions
Field Description
6:0
RDRQ[6:0]
Reduced Drive Port Q
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.