Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
152 Freescale Semiconductor
3.3.6 Port T
Port T is associated with two 4-channel timers (TIM0 and TIM1). Each pin is assigned to these modules
according to the following priority: TIM1/TIM0 > general-purpose I/O.
If the timer TIM0 is enabled, the channels configured for output compare are available on port T pins
PT[3:0]. If the timer TIM1 is enabled, the channels configured for output compare are available on port T
pins PT[7:4].
Refer to the TIM block description chapter for information on enabling and disabling the TIM module.
During reset, port T pins are configured as high-impedance inputs.
3.3.6.1 Port T I/O Register (PTT)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRTx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRTx) is set to 0 (input), a read returns the value of the pin.
3.3.6.2 Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
76543210
R
PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
W
TIM:
OC17 OC16 OC15 OC14 OC07 OC06 OC05 OC04
Reset 0 0 0 00000
Figure 3-36. Port T I/O Register (PTT)
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset u u u uuuuu
= Reserved or Unimplemented u = Unaffected by reset
Figure 3-37. Port T Input Register (PTIT)