Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 153
3.3.6.3 Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime.
This register configures port pins PT[7:0] as either input or output.
If the TIM0(1) module is enabled, each port pin configured for output compare is forced to be an output
and the associated Data Direction Register bit has no effect. If the associated timer output compare is
disabled, the corresponding DDRTx bit reverts to control the I/O direction of the associated pin.
If the TIM0(1) module is enabled, each port pin configured as an input capture has the corresponding
DDRTx bit controlling the I/O direction of the associated pin.
3.3.6.4 Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
76543210
R
DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 0 0 0 00000
Figure 3-38. Port T Data Direction Register (DDRT)
Table 3-27. DDRT Field Descriptions
Field Description
7:0
DDRT[7:0]
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
76543210
R
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W
Reset 0 0 0 00000
Figure 3-39. Port T Reduced Drive Register (RDRT)
Table 3-28. RDRT Field Descriptions
Field Description
7:0
RDRT[7:0]
Reduced Drive Port T
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.