Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 155
3.3.7 Port U
Port U is associated with one 4-channel timer (TIM2) and the pulse width modulator (PWM) module. Each
pin is assigned to these modules according to the following priority: TIM2/PWM > general-purpose I/O.
If the timer TIM2 is enabled, the channels configured for output compare are available on port U pins
PU[3:0]. Refer to the TIM block description chapter for information on enabling and disabling the TIM
module.
When a PWM channel is enabled, the corresponding pin becomes a PWM output. Refer to the PWM block
description chapter for information on enabling and disabling the PWM channels.
If both PWM and TIM2 are enabled simultaneously, the pin functionality is determined by the
configuration of the MODRR bits
During reset, port U pins are configured as high-impedance inputs.
3.3.7.1 Port U I/O Register (PTU)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRUx) is set to 0 (input), a read returns the value of the pin.
3.3.7.2 Port U Input Register (PTIU)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
76543210
R
PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0
W
PWM:
PW15 PW14 PW13 PW12 PW11 PW10
TIM2:
OC27 OC26 OC25 OC24
Reset 0 0 0 00000
Figure 3-42. Port U I/O Register (PTU)
76543210
R PTIU7 PTIU6 PTIU5 PTIU4 PTIU3 PTIU2 PTIU1 PTIU0
W
Reset u u u uuuuu
= Reserved or Unimplemented u = Unaffected by reset
Figure 3-43. Port U Input Register (PTIU)