Datasheet

Chapter 3 Port Integration Module (PIM9E128V1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 163
3.6 Interrupts
3.6.1 General
Port AD generates an edge sensitive interrupt if enabled. It offers sixteen I/O pins with edge triggered
interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector.
Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1)
or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or
wait mode.
A digital filter on each pin prevents pulses (Figure 3-52) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 3-51 and
Table 3-38).
Figure 3-51. Interrupt Glitch Filter on Port AD (PPS = 0)
Table 3-38. Pulse Detection Criteria
Pulse
Mode
STOP STOP
1
1
These values include the spread of the oscillator frequency over temperature,
voltage and process.
Unit Unit
Ignored t
pulse
<= 3 Bus Clock t
pulse
<= 3.2 µs
Uncertain 3 < t
pulse
< 4 Bus Clock 3.2 < t
pulse
< 10 µs
Valid t
pulse
>= 4 Bus Clock t
pulse
>= 10 µs
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
t
ifmin
t
ifmax